Abstract: A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

Abstract: A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed. current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

Abstract: A receiving circuit includes first input transistors of a first conductivity type including control terminals to which differential input signals are applied; load transistors of a second conductivity type connected between a first wiring to which a first voltage is supplied and first terminals of the first input transistors; second input transistors of the second conductivity type including control terminals to which the differential input signals are applied; a latch circuit connected between a second wiring to which a second voltage is supplied and first terminals of the second input transistors; and conversion transistors of the second conductivity type connected in parallel to the second input transistors, the conversion transistors including control terminals that are connected to output nodes to which the first input transistors and the load transistors are connected.

Abstract: A receiving circuit includes first input transistors of a first conductivity type including control terminals to which differential input signals are applied; load transistors of a second conductivity type connected between a first wiring to which a first voltage is supplied and first terminals of the first input transistors; second input transistors of the second conductivity type including control terminals to which the differential input signals are applied; a latch circuit connected between a second wiring to which a second voltage is supplied and first terminals of the second input transistors; and conversion transistors of the second conductivity type connected in parallel to the second input transistors, the conversion transistors including control terminals that are connected to output nodes to which the first input transistors and the load transistors are connected.

Abstract: The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion 20 driving output switching elements M1 and M2; a detecting portion 30 detecting that the voltage values of control terminals of the output switching elements M1 and M2 have exceeded the threshold voltage value; an auxiliary driving portion 40 being connected to the driving portion 20 and changing driving capability of the output switching elements M1 and M2 in accordance with the result of detection by the detecting portion 30.

Abstract: The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion 20 driving output switching elements M1 and M2; a detecting portion 30 detecting that the voltage values of control terminals of the output switching elements M1 and M2 have exceeded the threshold voltage value; an auxiliary driving portion 40 being connected to the driving portion 20 and changing driving capability of the output switching elements M1 and M2 in accordance with the result of detection by the detecting portion 30.