Abstract: A method used in forming memory circuitry comprises forming transistors of individual memory cells. The transistors individually comprise one source/drain region and another source/drain region. The one and another source/drain regions comprise conductively-doped monocrystalline semiconductive material. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Masking material is formed directly above the one and another source/drain regions. The masking material has openings there-through that extend to and are individually directly above individual of the one source/drain regions.

Abstract: An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

Abstract: An apparatus includes: a semiconductor substrate; an isolation region in the semiconductor substrate, the isolation region including an isolation trench filled with an insulating material therein; a plurality of island-shaped active regions in the semiconductor substrate surrounded by the isolation region; and a buried word-line having a bottom, the buried word-line at least passing across the isolation region between the plurality of active regions; wherein the isolation trench includes upper, middle and lower portions, each of the upper and lower portions has a substantially flat surface and the middle portion has a bulged surface.

Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.

Abstract: One semiconductor device manufacturing method includes forming, on a principal surface of a semiconductor substrate, multiple active regions which extend in an X-direction within the principal surface and are repeatedly arranged in a Y-direction, forming multiple trenches which extend in the Y-direction and define multiple active regions (silicon pillars) by respectively dividing the multiple active regions in the X-direction, forming element isolation regions by embedding an insulating film in the multiple trenches (T1), forming trenches which extend in the Y-direction after the element isolation regions are formed, and forming word lines by forming a gate insulating film, which covers the inner surfaces of the trenches, and further embedding a conductive film in the trenches. The trenches are formed by means of mutual self-alignment in the X-direction.

Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.

Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.

Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a first region and a second region other than the first region. A first mask is formed over the first region. The first mask has a first line-and-space pattern extending in a first direction. A first removing process is performed. The first removing process selectively removes the first region with the first mask to form a first groove extending in the first direction. The first removing process removes an upper part of the second region while a remaining part of the second region having a first surface facing upward. The bottom level of the first groove is higher than the level of the first surface.

Abstract: A coating film is formed on a member to be etched, which includes an amorphous carbon film and a silicon oxynitride film, by a spin coating method; a sidewall core is formed by pattering the coating film; a silicon oxide film is formed to cover at least the side surface of the sidewall core; and an organic anti-reflection film is formed on the silicon oxide film by a spin coating method. Thereafter, an embedded mask is formed to cover concave portions of the silicon oxide film by etching the organic anti-reflection film; exposed is a portion of the member to be etched which does not overlap the sidewall core or the embedded mask by etching the silicon oxide film; and the member to be etched is etched. Thus, it is possible to obtain a pattern with a size less than the photolithography resolution limit.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a first region and a second region other than the first region. A first mask is formed over the first region. The first mask has a first line-and-space pattern extending in a first direction. A first removing process is performed. The first removing process selectively removes the first region with the first mask to form a first groove extending in the first direction. The first removing process removes an upper part of the second region while a remaining part of the second region having a first surface facing upward. The bottom level of the first groove is higher than the level of the first surface.

Abstract: A method for forming trench gates is provided with a step of forming gate trenches on a semiconductor substrate, and a step of forming an element isolation region on the semiconductor substrate on which the gate trenches are formed. A step of channel doping within the gate trenches is performed before the element isolation region is formed and after the gate trenches are formed. The method for forming the trench gate is further provided with a step of forming a gate oxide film on the inner wall of the gate trenches, and a step of embedding a gate electrode material within the gate trenches.