Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.

Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.

Abstract: An object is to obtain a burn-in system which can speed up the burn-in not only in memory cell array portions but also in peripheral circuit and logic circuit portions. First, a wafer (3) to be evaluated is put in a constant temperature chamber (1a) and subjected to high temperature stress. The wafer (3) is then put in a constant temperature chamber (1b) and subjected to low temperature stress. The applications of the temperature stresses in the constant temperature chambers (1a) and (1b) may be repeatedly performed. When given temperature stresses have been applied to the wafer (3), the wafer (3) is conveyed to an evaluation unit (5). The evaluation unit (5) then checks whether failure exists in chips (30). If the evaluation determines that a chip (30) has a failure, whether to apply repair to the failure portion is decided and repair is applied if possible.