Patents by Inventor Hiromitsu Takeda

Hiromitsu Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11273409
    Abstract: Provided is a catalyst device that makes it possible to efficiently purify exhaust gas. A catalyst device that comprises: a carrier that is formed by stacking and rolling a metal-foil-shaped flat plate and a metal-foil-shaped corrugated plate and that carries a catalyst; and an outer cylinder that houses the carrier and supports the carrier such that one end part of the carrier is oriented toward an exhaust gas upstream side and another end part of the carrier is oriented toward an exhaust gas downstream side. The flat plate and the corrugated plate have a plurality of holes and are covered by a coating film that includes a catalyst substance. The coating film that covers the downstream side of the holes is thicker than the coating film that covers the upstream side of the holes.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 15, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Kazuhisa Maeda, Hiromitsu Takeda, Hiroyuki Horimura
  • Publication number: 20210291113
    Abstract: Provided is a catalyst device that makes it possible to efficiently purify exhaust gas. A catalyst device that comprises: a carrier that is formed by stacking and rolling a metal-foil-shaped flat plate and a metal-foil-shaped corrugated plate and that carries a catalyst; and an outer cylinder that houses the carrier and supports the carrier such that one end part of the carrier is oriented toward an exhaust gas upstream side and another end part of the carrier is oriented toward an exhaust gas downstream side. The flat plate and the corrugated plate have a plurality of holes and are covered by a coating film that includes a catalyst substance. The coating film that covers the downstream side of the holes is thicker than the coating film that covers the upstream side of the holes.
    Type: Application
    Filed: August 6, 2019
    Publication date: September 23, 2021
    Inventors: Kazuhisa Maeda, Hiromitsu Takeda, Hiroyuki Horimura
  • Patent number: 11105959
    Abstract: An infrared-shielding nanoparticle dispersion has a property whereby visible light is adequately transmitted, and light in the near-infrared region is adequately shielded. The infrared-shielding nanoparticles include a plural aggregate of electroconductive particles composed of a tungsten oxide expressed by the general formula WyOz (where W is tungsten, O is oxygen, and 2.2?z/y?2.999), and/or a composite tungsten oxide expressed by the general formula MxWyOz (where M is one or more elements selected from H, alkali metals, alkaline-earth metals, rare earth elements, Mg, Zr, Cr, Mn, Fe, Ru, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Al, Ga, In, Tl, Si, Ge, Sn, Pb, Sb, B, F, P, S, Se, Br, Te, Ti, Nb, V, Mo, Ta, Re, Be, Hf, Os, Bi, and I; W is tungsten; O is oxygen; 0.001?x/y?1.1; and 2.2?z/y?3.0).
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 31, 2021
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Hiromitsu Takeda, Kenji Adachi
  • Publication number: 20180188419
    Abstract: An infrared-shielding nanoparticle dispersion has a property whereby visible light is adequately transmitted, and light in the near-infrared region is adequately shielded. The infrared-shielding nanoparticles include a plural aggregate of electroconductive particles composed of a tungsten oxide expressed by the general formula WyOz (where W is tungsten, O is oxygen, and 2.2?z/y?2.999), and/or a composite tungsten oxide expressed by the general formula MxWyOz (where M is one or more elements selected from H, alkali metals, alkaline-earth metals, rare earth elements, Mg, Zr, Cr, Mn, Fe, Ru, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Al, Ga, In, Tl, Si, Ge, Sn, Pb, Sb, B, F, P, S, Se, Br, Te, Ti, Nb, V, Mo, Ta, Re, Be, Hf, Os, Bi, and I; W is tungsten; O is oxygen; 0.001?x/y?1.1; and 2.2?z/y?3.0).
    Type: Application
    Filed: February 23, 2018
    Publication date: July 5, 2018
    Inventors: Hiromitsu TAKEDA, Kenji ADACHI
  • Patent number: 9991195
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 5, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Takeda
  • Publication number: 20170133312
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventor: Hiromitsu TAKEDA
  • Patent number: 9589882
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Takeda
  • Publication number: 20160190058
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 30, 2016
    Inventor: Hiromitsu TAKEDA
  • Publication number: 20160148895
    Abstract: A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being provided with a plurality of leads, after the providing of the wiring substrate, arranging a semiconductor chip with a main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate, after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires, and after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 26, 2016
    Inventors: Akira OHASHI, Akira UMEZU, Hiromitsu TAKEDA
  • Patent number: 9275940
    Abstract: A semiconductor device is provided which complies with restrictions on layout on a mounting substrate side. The semiconductor device includes a wiring substrate having a plurality of bonding leads at an upper surface having a rectangular shape, a semiconductor chip mounted over the upper surface of the wiring substrate, and having a plurality of electrode pads at a main surface having a rectangular shape similar to a square shape, and a plurality of metal wires for coupling the bonding leads of the wiring substrate to the electrode pads of the semiconductor chip. In a BGA, the metal wires are arranged at three sides of a main surface of the semiconductor chip, the bonding leads are provided in lines at the upper surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip, and the metal wires are coupled to the bonding leads.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Ohashi, Akira Umezu, Hiromitsu Takeda
  • Publication number: 20150153478
    Abstract: Provided is an infrared-shielding nanoparticle dispersion that has a property whereby visible light is adequately transmitted, and light in the near-infrared region is adequately shielded. The infrared-shielding nanoparticles include a plural aggregate of electroconductive particles composed of a tungsten oxide expressed by the general formula WyOz (where W is tungsten, O is oxygen, and 2.2?z/y?2.999), and/or a composite tungsten oxide expressed by the general formula MxWyOz (where M is one or more elements selected from H, alkali metals, alkaline-earth metals, rare earth elements, Mg, Zr, Cr, Mn, Fe, Ru, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Al, Ga, In, Tl, Si, Ge, Sn, Pb, Sb, B, F, P, S, Se, Br, Te, Ti, Nb, V, Mo, Ta, Re, Be, Hf, Os, Bi, and I; W is tungsten; O is oxygen; 0.001?x/y?1.1; and 2.2?z/y?3.0).
    Type: Application
    Filed: February 5, 2015
    Publication date: June 4, 2015
    Inventors: Hiromitsu TAKEDA, Kenji ADACHI
  • Patent number: 8980135
    Abstract: An object of the present invention is to provide an infrared-shielding nanoparticle dispersion that has a property whereby visible light is adequately transmitted, and light in the near-infrared region is adequately shielded; an infrared-shielding body manufactured using the infrared-shielding nanoparticle dispersion; a method for manufacturing infrared-shielding nanoparticles that are used in the infrared-shielding nanoparticle dispersion; and infrared-shielding nanoparticles manufactured using the method for manufacturing infrared-shielding nanoparticles.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Hiromitsu Takeda, Kenji Adachi
  • Publication number: 20150021749
    Abstract: A semiconductor device is provided which complies with restrictions on layout on a mounting substrate side. The semiconductor device includes a wiring substrate having a plurality of bonding leads at an upper surface having a rectangular shape, a semiconductor chip mounted over the upper surface of the wiring substrate, and having a plurality of electrode pads at a main surface having a rectangular shape similar to a square shape, and a plurality of metal wires for coupling the bonding leads of the wiring substrate to the electrode pads of the semiconductor chip. In a BGA, the metal wires are arranged at three sides of a main surface of the semiconductor chip, the bonding leads are provided in lines at the upper surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip, and the metal wires are coupled to the bonding leads.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 22, 2015
    Inventors: Akira Ohashi, Akira Umezu, Hiromitsu Takeda
  • Patent number: 8466565
    Abstract: A substrate has a plurality of pads formed over one surface of a base, and an insulating film which is formed thereon and has a plurality of openings formed therein so as to expose each of the pads, wherein the openings of the insulating film are formed so that, in each pad formed at the corner of the base, among the plurality of pads, a first peripheral portion which composes a portion of the pad more closer to the corner and more distant away from the center of the base is covered by the insulating film, and so that a second peripheral portion which composes a portion of the pad more closer to the center as compared with the first peripheral portion is exposed in the opening.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: June 18, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Takeda
  • Patent number: 8083847
    Abstract: To provide an infrared-shielding body sufficiently transmitting visible rays, having no half-mirror shaped appearance, requiring no large-scale apparatus when forming a film on a substrate, efficiently shutting invisible near-infrared rays with wavelength range of 780 nm or more, while eliminating a heat treatment at high temperature after film formation, and having a spectral characteristic such as transparency with no change of color tone. The starting material, which is a mixture containing a predetermined amount of a tungsten compound, is heated at 550° C. in a reductive atmosphere for 1 hour, then cooled to room temperature once in an argon atmosphere, thus producing powder of W18O49. Then, the powder, the solvent, and the dispersant are mixed, then subjected to dispersion treatment to obtain a dispersion solution. The dispersion solution and a UV-curable hardcoat resin are mixed to obtain a solution of fine particle dispersion of infrared-shielding material.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: December 27, 2011
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Hiromitsu Takeda, Kenji Adachi
  • Patent number: 7935389
    Abstract: A printer is provided which sprays ink from nozzles to print recording paper P.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: May 3, 2011
    Assignee: Sony Corporation
    Inventors: Takanori Takahashi, Kenji Okamoto, Soichi Kuwahara, Yuji Yakura, Shinichi Horii, Yoshiaki Haba, Hiromitsu Takeda
  • Publication number: 20110091720
    Abstract: An object is to provide a fiber that absorbs heat with good efficiency, has excellent transparency and heat-retaining properties, and does not compromise the design characteristics of a textile product, and to provide a textile product in which the fiber is used. Hexaboride nanoparticles, a dispersion medium, and a dispersion agent for dispersing the nanoparticles are mixed together. The mixture is dispersed and dried to obtain a dispersion powder. The resulting dispersion powder is added to thermoplastic resin pellets, uniformly mixed, and thereafter melted and kneaded to obtain a master batch containing a heat-absorbing component. The master batch containing a heat-absorbing component is mixed with a similarly prepared master batch to which inorganic nanoparticles has not been added, and the mixture is melted, spun, and drawn to manufacture a multifilament yarn. The multifilament yarn is cut to fabricate staples, and the staples are used to manufacture a spun yarn having heat-absorbing effects.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 21, 2011
    Applicant: SUMITOMO METAL MINING CO., LTD.
    Inventors: Kayo Yabuki, Kenichi Fujita, Hiromitsu Takeda, Kenji Adachi
  • Patent number: 7927696
    Abstract: The visible light absorbing film according to the present invention is formed by a visible light absorbing ink having been coated on one side or both sides of a substrate which has solar radiation reflecting properties and whose visible light reflectance is 10% or more, and is characterized in that the degree of reduction of visible light reflectance is 0.9 or less as defined by degree of reduction of visible light reflectance=[visible light reflectance (%) after coating of the ink]/[visible light reflectance (%) before coating of the ink], and the degree of reduction of solar radiation reflectance is 0.25 or more as defined by degree of reduction of solar radiation reflectance=[solar radiation reflectance (%) after coating of the ink]/[solar radiation reflectance (%) before coating of the ink].
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: April 19, 2011
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventors: Hiromitsu Takeda, Kayo Yabuki
  • Publication number: 20100258953
    Abstract: A substrate has a plurality of pads formed over one surface of a base, and an insulating film which is formed thereon and has a plurality of openings formed therein so as to expose each of the pads, wherein the openings of the insulating film are formed so that, in each pad formed at the corner of the base, among the plurality of pads, a first peripheral portion which composes a portion of the pad more closer to the corner and more distant away from the center of the base is covered by the insulating film, and so that a second peripheral portion which composes a portion of the pad more closer to the center as compared with the first peripheral portion is exposed in the opening.
    Type: Application
    Filed: March 23, 2010
    Publication date: October 14, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiromitsu TAKEDA
  • Publication number: 20090135224
    Abstract: A liquid discharger wherein, when a liquid discharge operation on a discharge object is started, a cap is opened in order to wipe a liquid discharge surface by bringing a cleaning member into contact with and moving the cleaning member along the liquid discharge surface, then liquid drops are preliminarily discharged to the cap from liquid discharge nozzles after the cleaning member has moved along the liquid discharge surface, and then, while the cap is withdrawn from the liquid discharge surface, prior to discharging liquid onto the discharge object, liquid drops are preliminarily discharged to a platen plate from the liquid discharge nozzles.
    Type: Application
    Filed: May 27, 2008
    Publication date: May 28, 2009
    Applicant: Sony Corporation
    Inventors: Yuji Yakura, Takanori Takahashi, Hiroshi Udagawa, Hiromitsu Takeda, Toshiki Kagami, Shinichi Horii