Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Abstract: In an IGBT region of a semiconductor device, a barrier region is disposed above a drift layer, and a contact trench is disposed between adjacent gate trenches in a semiconductor substrate. A first electrode is embedded in the contact trench. A connecting region is disposed between a bottom surface of the contact trench and the barrier region, and is connected to the barrier region and the first electrode. Further, the emitter region and the contact region are arranged in a direction different from an arrangement direction of the gate trenches. Thus, the semiconductor device can be miniaturized.

Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, a first region formed in a surface layer of the first main surface, a drift layer disposed adjacent to the first region, a charge accumulation region having a higher concentration than the drift region, and a trench gate including a trench penetrating the first region and the charge accumulation region, and a gate electrode formed in the trench. The trench gate includes a main trench having a gate electrode to which a gate voltage is applied, and a dummy trench having a gate electrode to which a voltage different from the main trench is applied. The main trench and the dummy trench sandwiches the charge accumulation region, and a contact area S1 between the dummy trench and the charge accumulation region is larger than a contact area S2 between the main trench and the charge accumulation region.

Abstract: On a front surface side of an n? semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 ?m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.

Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.

Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.

Abstract: A semiconductor device includes a semiconductor substrate provided with an IGBT cell having a collector region and a diode cell having a cathode region, a first defect layer and a second defect layer in a drift region. A region present in the drift region and surrounded by an interface between the IGBT cell and the diode cell orthogonal to a first principal plane, and a plane passing through a boundary between the collector region and the cathode region on a boundary line along an interface between the collector region and the drift region and crossing the first principal plane at an angle of 45 degrees is referred to as a boundary region. The diode cell satisfies a relationship of SD1>S, in which S is an area occupied by the boundary region and SD1 is an area occupied by the diode cell in a surface of the drift region.

Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad. The first control pad is electrically connected to the gate electrode and applied with a voltage controlling the switching element to switch on or switch off. The second control pad provides a current path of a control current flowing between the first control pad and the second control pad when the switching element is in a switch-on state. One of the first control pad or the second control pad includes two pad components and a remaining one of the first control pad or the second control pad is disposed between the two pad components of the one of the first control pad or the second control pad.

Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.

Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces, a first region formed in a surface layer of the first main surface, a drift layer disposed adjacent to the first region, a charge accumulation region having a higher concentration than the drift region, and a trench gate including a trench penetrating the first region and the charge accumulation region, and a gate electrode formed in the trench. The trench gate includes a main trench having a gate electrode to which a gate voltage is applied, and a dummy trench having a gate electrode to which a voltage different from the main trench is applied. The main trench and the dummy trench sandwiches the charge accumulation region, and a contact area S1 between the dummy trench and the charge accumulation region is larger than a contact area S2 between the main trench and the charge accumulation region.

Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad. The first control pad is electrically connected to the gate electrode and applied with a voltage controlling the switching element to switch on or switch off. The second control pad provides a current path of a control current flowing between the first control pad and the second control pad when the switching element is in a switch-on state. One of the first control pad or the second control pad includes two pad components and a remaining one of the first control pad or the second control pad is disposed between the two pad components of the one of the first control pad or the second control pad.

Abstract: A semiconductor device includes a semiconductor substrate provided with an IGBT cell having a collector region and a diode cell having a cathode region, a first defect layer and a second defect layer in a drift region. A region present in the drift region and surrounded by an interface between the IGBT cell and the diode cell orthogonal to a first principal plane, and a plane passing through a boundary between the collector region and the cathode region on a boundary line along an interface between the collector region and the drift region and crossing the first principal plane at an angle of 45 degrees is referred to as a boundary region. The diode cell satisfies a relationship of SD1>S, in which S is an area occupied by the boundary region and SD1 is an area occupied by the diode cell in a surface of the drift region.

Abstract: On a front surface side of an n? semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n+ emitter region are the IGBT emitter region and the p base layers not having the n+ emitter region are the FWD anode region. A lateral width of an n+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n+ cathode region is 50 ?m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.

Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.

Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

Abstract: A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.

Abstract: A semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the semiconductor device including an electrode portion having a potential other than a gate potential, and an electrode pad that is disposed on a front face of a semiconductor substrate, wherein the electrode pad is used as a terminal to apply a predetermined voltage to gate insulator films, in screening that is executed by applying the predetermined voltage to the gate insulator films respectively in contact with the gate electrode connected to the electrode pad and that is executed before the electrode pad is short-circuited to the electrode portion.

Abstract: A fabrication method of a semiconductor device that includes trench gate structures each having a gate electrode extending in a depth-direction of an element, where first trench gate structures contribute to controlling the element and second trench gate structures do not contribute. The fabrication method includes forming the trench gate structures on a front face of a semiconductor substrate; forming on the front face, an electrode pad connected to the gate electrode of at least one trench gate structure; executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad; and forming the second trench gate structures having the gate electrodes connected to the electrode pad, by short-circuiting the electrode portion to the electrode pad after executing screening.