Abstract: A universal-serial-bus (“USB”) hub circuit includes a switch circuit connected to a USB hub section and a plurality of upstream terminals each of which is adapted to be connected to computers. The USB hub circuit also includes a selector that operates the switch circuit to couple the USB hub section to a selected upstream terminal. A display device incorporates the USB hub circuit. A video sync signal output by an active host computer coupled to one of the upstream terminals determines which upstream terminal is to be coupled to the USB hub circuit.

Abstract: The invention relates to a multiscanning type display apparatus having a matrix drive type display device for displaying picture signals, a picture signal supplying section for supplying picture signals to the display device, a synchronization signal supplying section for outputting synchronization signals included in the above mentioned picture signals, and a resolution power converting section for converting the resolution of the above mentioned picture signals to the resolution of the above mentioned display device.

Abstract: A video display device for displaying a wide range of video signals which allows the user to freely set the screen display width and position. A request for adjusting the horizontal display width, vertical display width, horizontal display position, and vertical display position is made through a key circuit, and a microcomputer determines the state of the key circuit. The microcomputer then recalculates the horizontal expansion rate and vertical expansion rate of a scan converter, and send recalculated data to the scan converter and a PLL circuit. The scan converter and the PLL circuit converts signals to the number of picture elements displayable on the video display device in response to a request for adjustment, and changes the phase of the enable signal which indicates a display period of the video display device to adjust horizontal and vertical display positions.

Abstract: A/D converters (15-17), a PLL circuit (18), a scan conversion circuit (1), counters (4 and 5), an OR circuit (3), flip-flops (7-13) for comparing a phase of an output signal from the OR circuit (3) with a phase of an enable signal, and a CPU (14) are provided in a LCD apparatus so that settings in the scan conversion circuit (1), counter (4 and 5), and PLL circuit (18) can be changed responsive to outputs from the flip-flops (10-13), whereby a location and a size of a picture displayed on the LCD as well as a sampling clock frequency used in the A/D conversion can be automatically adjusted.