Patents by Inventor Hiromitsu Tsunoda

Hiromitsu Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140102931
    Abstract: A pressure-sensitive adhesive tape package is described in which while easiness in applying the adhesive tape is pursued, an effect of saving in resources can be obtained. The pressure-sensitive adhesive tape package accommodates an adhesive tape having a support and an adhesive agent layer provided on one surface of the support, and includes a release sheet releasably attached to the adhesive agent layer. Moreover, in the pressure-sensitive adhesive tape package, the release sheet is bent along a predetermined bending line with the adhesive tape, and the adhesive tape is sealed inside of the bent release sheet.
    Type: Application
    Filed: November 20, 2013
    Publication date: April 17, 2014
    Applicant: Hisamitsu Pharmaceutical Co., Inc.
    Inventors: Isao MIYACHI, Yuichi TAKANO, Hiromitsu TSUNODA
  • Patent number: 8616371
    Abstract: A pressure-sensitive adhesive tape package is described in which while easiness in applying the adhesive tape is pursued, an effect of saving in resources can be obtained. The pressure-sensitive adhesive tape package accommodates an adhesive tape having a support and an adhesive agent layer provided on one surface of the support, and includes a release sheet releasably attached to the adhesive agent layer. Moreover, in the pressure-sensitive adhesive tape package, the release sheet is bent along a predetermined bending line with the adhesive tape, and the adhesive tape is sealed inside of the bent release sheet.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: December 31, 2013
    Assignee: Hisamitsu Pharmaceutical Co., Ltd.
    Inventors: Isao Miyachi, Yuichi Takano, Hiromitsu Tsunoda
  • Patent number: 8302051
    Abstract: A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Tsunoda
  • Publication number: 20110253303
    Abstract: A pressure-sensitive adhesive tape package is described in which while easiness in applying the adhesive tape is pursued, an effect of saving in resources can be obtained. The pressure-sensitive adhesive tape package accommodates an adhesive tape having a support and an adhesive agent layer provided on one surface of the support, and includes a release sheet releasably attached to the adhesive agent layer. Moreover, in the pressure-sensitive adhesive tape package, the release sheet is bent along a predetermined bending line with the adhesive tape, and the adhesive tape is sealed inside of the bent release sheet.
    Type: Application
    Filed: December 14, 2009
    Publication date: October 20, 2011
    Applicant: HISAMITSU PHARMACEUTICAL CO., INC.
    Inventors: Isao Miyachi, Yuichi Takano, Hiromitsu Tsunoda
  • Publication number: 20110066991
    Abstract: A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiromitsu TSUNODA
  • Patent number: D668766
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Hisamitsu Pharmaceutical Co., Inc
    Inventors: Isao Miyachi, Yuichi Takano, Hiromitsu Tsunoda