Abstract: First data (“00”, “01”, “10”, “11”) corresponding to threshold voltages of four values (1 V, 2 V, 3 V, 4 V) are stored in the individual memory cells of an EEPROM. Upon reading, a decoder circuit assigns bits so that neighboring first data have only one different bit in their two-bit architectures, thus converting the first data into second data (“00”, “01”, “11”, and “10”), and outputting the second data as storage data of the memory cells. Even when multiple-valued storage data are lost from the EEPROM due to data errors arising from deterioration of memory cells which have inevitably occurred after repetitive uses, error detection and error correction can be efficiently and accurately done. Of course, the data to be stored is not limited to 2-bit data, but the present invention can also be applied to multiple-valued data of 3 bits or more.