Patents by Inventor Hiromu Enomoto

Hiromu Enomoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4888623
    Abstract: Electrostatical breakage of a semiconductor device, including an epitaxial layer and a buried layer thereunder, connected to an outer signal terminal, can be prevented by forming an impurity region in the epitaxial layer so as to form a PN junction between the buried layer and the impurity region. The impurity region is connected to a power source or ground.
    Type: Grant
    Filed: October 12, 1988
    Date of Patent: December 19, 1989
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Yoshiki Shimauchi, Akinori Tahara
  • Patent number: 4883975
    Abstract: A Schmitt trigger circuit has a first transistor for inversion having a base supplied with an input voltage. A level shift diode shifts an emitter voltage of the first transistor from a reference level, and a second transistor for switching has a collector and an emitter respectively coupled to an anode and a cathode of the level shift diode. The emitter of the second transistor is coupled to a first power source voltage. A switching part is coupled between a base of the second transistor and a second power source voltage higher than the first power source voltage, for controlling switching of the second transistor. An output circuit is coupled between the first and second power source voltages and supplied with the input voltage through the first transistor for outputting the output voltage. The switching part is controlled responsive to a voltage from the output circuit so as to close when the logic level of this voltage is the high level, thereby turning the second transistor ON.
    Type: Grant
    Filed: November 8, 1988
    Date of Patent: November 28, 1989
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Hiromu Enomoto, Hirofumi Dohgome, Masao Kumagai, Toru Nakamura, Kimitaka Yoshiyama
  • Patent number: 4774620
    Abstract: A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.
    Type: Grant
    Filed: September 17, 1987
    Date of Patent: September 27, 1988
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Masao Kumagai, Akinori Tahara
  • Patent number: 4703202
    Abstract: A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.
    Type: Grant
    Filed: February 11, 1985
    Date of Patent: October 27, 1987
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Akinori Tahara, Masao Kumagai
  • Patent number: 4680600
    Abstract: A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region.
    Type: Grant
    Filed: October 21, 1986
    Date of Patent: July 14, 1987
    Assignee: Fujitsu Limited
    Inventors: Akinori Tahara, Hiromu Enomoto, Yasushi Yasuda
  • Patent number: 4567380
    Abstract: A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.
    Type: Grant
    Filed: June 24, 1983
    Date of Patent: January 28, 1986
    Assignee: Fujitsu Limited
    Inventors: Yasushi Yasuda, Hiromu Enomoto, Yoshiki Shimauchi, Akinori Tahara
  • Patent number: 4449063
    Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: May 15, 1984
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ohmichi, Hiromu Enomoto, Yasushi Yasuda, Yoshiharu Mitono, Taketo Imaizumi
  • Patent number: 4409495
    Abstract: A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.
    Type: Grant
    Filed: May 29, 1981
    Date of Patent: October 11, 1983
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yoshiharu Mitono, Yasushi Yasuda, Taketo Imaizumi, Hiroshi Ohta
  • Patent number: 4388755
    Abstract: A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiring patterns. A number of bipolar transistors each having plural emitter regions, is formed in a predetermined region, or portion, of a semiconductor substrate by employing a common master pattern, and the plural emitter regions of the respective bipolar transistors are selectively connected by the associated wiring patterns of each thereof to form corresponding bipolar transistors of different, predetermined D.C. characteristics. When manufacturing many different kinds of semiconductor devices by the master slice method, the area which would be wasted on the semiconductor substrate by prior art techniques is greatly reduced, thus providing for enhanced area efficiency.
    Type: Grant
    Filed: November 17, 1980
    Date of Patent: June 21, 1983
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Yoshiharu Mitono, Taketo Imaizumi, Hitoshi Ohmichi
  • Patent number: 4276556
    Abstract: A semiconductor device including a diode and a bipolar transistor which are connected to each other and formed in an isolated area of a semiconductor layer has a diffused region formed between a base region of the bipolar transistor and a formation region of the diode across the isolated area. The diffused region has the same conductivity type as that of the base region, so that a PNPN diode effect does not occur.
    Type: Grant
    Filed: November 15, 1979
    Date of Patent: June 30, 1981
    Assignee: Fujitsu Limited
    Inventors: Hiromu Enomoto, Yasushi Yasuda, Hitoshi Ohmichi, Yoshiharu Mitono