Patents by Inventor Hiromu Iwamoto
Hiromu Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5220559Abstract: An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.Type: GrantFiled: August 30, 1989Date of Patent: June 15, 1993Assignee: Fujitsu LimitedInventors: Hiroyuki Tsuzuki, Hideichi Endo, Takashi Kawasaki, Toshiharu Matsuda, Kazuo Asakawa, Hideki Kato, Hideki Yoshizawa, Hiroki Iciki, Hiromu Iwamoto, Chikara Tsuchiya, Katsuya Ishikawa, Yoshihide Sugiura
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Patent number: 5216746Abstract: An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors.Type: GrantFiled: February 28, 1990Date of Patent: June 1, 1993Assignee: Fujitsu LimitedInventors: Hideki Yoshizawa, Hiroki Iciki, Hideki Kato, Kazuo Asakawa, Yoshihide Sugiura, Hiroyuki Tsuzuki, Hideichi Endoh, Takashi Kawasaki, Toshiharu Matsuda, Hiromu Iwamoto, Chikara Tsuchiya, Katsuya Ishikawa
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Patent number: 5142666Abstract: A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.Type: GrantFiled: February 28, 1990Date of Patent: August 25, 1992Assignee: Fujitsu LimitedInventors: Hideki Yoshizawa, Hiroki Iciki, Hideki Kato, Kazuo Asakawa, Yoshihide Sugiura, Hiroyuki Tsuzuki, Hideichi Endoh, Takashi Kawasaki, Toshiharu Matsuda, Hiromu Iwamoto, Chikara Tsuchiya, Katsuya Ishikawa
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Patent number: 5131072Abstract: An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation.Type: GrantFiled: April 30, 1990Date of Patent: July 14, 1992Assignee: Fujitsu, Ltd.Inventors: Hideki Yoshizawa, Hiroki Iciki, Hideki Kato, Yoshihide Sugiura, Kazuo Asakawa, Hiroyuki Tsuzuki, Hideichi Endo, Takashi Kawasaki, Toshiharu Matsuda, Chikara Tsuchiya, Katsuya Ishikawa, Hiromu Iwamoto
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Patent number: 4544912Abstract: A D/A converter of the resistor ladder type provided with full-scale switching circuits between the output terminal of the series connected resistors and ground for selecting the value of resistance of the full-scale control resistor, thereby selecting the value of the full-scale voltage.Type: GrantFiled: January 27, 1984Date of Patent: October 1, 1985Assignee: Fujitsu LimitedInventors: Hiromu Iwamoto, Haruo Tamada
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Patent number: 4456840Abstract: A comparator circuit providing a hysteresis characteristic which does not change a hysteresis width even if a power supply voltage changes is disclosed. The comparator circuit comprises a differential amplifier including an input terminal, a reference terminal and an output terminal; an input voltage terminal to which an input voltage is applied; a reference voltage terminal to which a reference voltage is applied; at least one level shift means connected between said input voltage terminal and said input terminal, or between said reference voltage terminal and said reference terminal; a current source means connected to the output of said level shift means; and control means for controlling the current value of said current source means in accordance with the output level of said output terminal.Type: GrantFiled: December 11, 1981Date of Patent: June 26, 1984Assignee: Fujitsu LimitedInventors: Tetsuo Ide, Hiromu Iwamoto