Patents by Inventor Hiromu Shiomi
Hiromu Shiomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240068125Abstract: An SiC single-crystal growth apparatus and a method of growing an SiC crystal are provided capable of reducing variations in the temperature distribution in the seed crystal and/or reducing deformation of, and/or damage to, the seed crystal, thereby growing an SiC single crystal with reduced defects and/or cracks. An SiC single-crystal growth apparatus (1) includes: a heating vessel (10) including a source material-containing portion (12) adapted to contain a solid source material of SiC in one of an upper portion or a lower portion (e.g., on the bottom portion 13) of an interior space S defined by a cylindrical peripheral side portion (14), and including a seat (17) located in another portion located opposite to said one portion (e.g.Type: ApplicationFiled: January 18, 2022Publication date: February 29, 2024Applicant: SEC CARBON, Ltd.Inventor: Hiromu SHIOMI
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Publication number: 20220059658Abstract: A silicon carbide epitaxial layer includes a first silicon carbide layer, a second silicon carbide layer, a third silicon carbide layer, and a fourth silicon carbide layer. A nitrogen concentration of the second silicon carbide layer is increased from the first silicon carbide layer toward the third silicon carbide layer. A value obtained by dividing, by a thickness of the second silicon carbide layer, a value obtained by subtracting a nitrogen concentration of the first silicon carbide layer from a nitrogen concentration of the third silicon carbide layer is less than or equal to 6×1023 cm?4. Assuming that the nitrogen concentration of the third silicon carbide layer is N cm?3; and a thickness of the third silicon carbide layer is X ?m, X and N satisfy a Formula 1.Type: ApplicationFiled: August 8, 2019Publication date: February 24, 2022Inventors: Tsutomu HORI, Hiromu SHIOMI, Takaya MIYASE
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Patent number: 11233125Abstract: A silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type, a third impurity region having the first conductivity type, and a fourth impurity region provided between a second main surface and a bottom surface and having the second conductivity type. The first impurity region has a first region being in contact with the second impurity region and having a first impurity concentration, a second region being continuous to the first region, provided between the first region and the second main surface, and having a second impurity concentration lower than the first impurity concentration, and a third region being continuous to the first region and having a third impurity concentration higher than the first impurity concentration. A side surface is in contact with the third region, the second impurity region, and the third impurity region.Type: GrantFiled: May 10, 2019Date of Patent: January 25, 2022Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hiromu Shiomi
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Patent number: 10903374Abstract: A semiconductor device includes a first JTE region formed around an active portion, a second JTE region formed around the first JTE region, and a third JTE region formed around the second JTE region. The first, second, and third JTE regions are doped with an impurity of a second conductivity type different from a first conductivity type. A concentration ratio R21 “(concentration of impurity in second JTE region)/(concentration of impurity in first JTE region)” and a concentration ratio R32 “(concentration of impurity in third JTE region)/(concentration of impurity in second JTE region)” are 0.50 or greater and 0.65 or less. A width W1 of the first JTE region, a width W2 of the second JTE region, and a width W3 of the third JTE region are 130 ?m or greater and 190 ?m or less.Type: GrantFiled: November 13, 2017Date of Patent: January 26, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Hidenori Kitai, Hiromu Shiomi, Kenji Fukuda
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Publication number: 20200279921Abstract: A silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type, a third impurity region having the first conductivity type, and a fourth impurity region provided between a second main surface and a bottom surface and having the second conductivity type. The first impurity region has a first region being in contact with the second impurity region and having a first impurity concentration, a second region being continuous to the first region, provided between the first region and the second main surface, and having a second impurity concentration lower than the first impurity concentration, and a third region being continuous to the first region and having a third impurity concentration higher than the first impurity concentration. A side surface is in contact with the third region, the second impurity region, and the third impurity region.Type: ApplicationFiled: May 10, 2019Publication date: September 3, 2020Applicant: Sumitomo Electric Industries, Ltd.Inventor: Hiromu SHIOMI
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Publication number: 20200251600Abstract: A semiconductor device includes a first JTE region formed around an active portion, a second JTE region formed around the first JTE region, and a third JTE region formed around the second JTE region. The first, second, and third JTE regions are doped with an impurity of a second conductivity type different from a first conductivity type. A concentration ratio R21 “(concentration of impurity in second JTE region)/(concentration of impurity in first JTE region)” and a concentration ratio R32 “(concentration of impurity in third JTE region)/(concentration of impurity in second JTE region)” are 0.50 or greater and 0.65 or less. A width W1 of the first JTE region, a width W2 of the second JTE region, and a width W3 of the third JTE region are 130 ?m or greater and 190 ?m or less.Type: ApplicationFiled: November 13, 2017Publication date: August 6, 2020Inventors: Hidenori KITAI, Hiromu SHIOMI, Kenji FUKUDA
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Patent number: 10707299Abstract: The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.Type: GrantFiled: May 14, 2015Date of Patent: July 7, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hiromu Shiomi
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Patent number: 10453952Abstract: The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.Type: GrantFiled: September 8, 2016Date of Patent: October 22, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Hideto Tamaso, Kenji Fukuda
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Patent number: 10424642Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.Type: GrantFiled: September 8, 2016Date of Patent: September 24, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
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Publication number: 20180331209Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.Type: ApplicationFiled: September 8, 2016Publication date: November 15, 2018Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
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Publication number: 20180315813Abstract: The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.Type: ApplicationFiled: September 8, 2016Publication date: November 1, 2018Inventors: Hiromu Shiomi, Hidenori Kitai, Hideto Tamaso, Kenji Fukuda
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Publication number: 20180286979Abstract: A step of forming a silicon carbide substrate includes steps of: forming a first impurity region having a first conductivity type by epitaxial growth; forming an embedded region by performing ion implantation into the first impurity region, the embedded region having a second conductivity type different from the first conductivity type, the embedded region being disposed cyclically; and forming a second impurity region by epitaxial growth, the second impurity region being in contact with the first impurity region and the embedded region, the second impurity region having the second conductivity type, the second impurity region having an impurity concentration lower than an impurity concentration of the embedded region. A trench is formed to have a side portion and a bottom portion. The trench is disposed at the same cycle as the embedded region.Type: ApplicationFiled: May 31, 2018Publication date: October 4, 2018Inventor: Hiromu Shiomi
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Patent number: 10062750Abstract: An active region through which current flows in a semiconductor device includes an n?-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n?-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n?-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n?-type layer and that of the n?-type silicon carbide epitaxial layer.Type: GrantFiled: August 4, 2017Date of Patent: August 28, 2018Assignees: FUJI ELECTRIC CO., LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yusuke Kobayashi, Hiromu Shiomi, Shinya Kyogoku, Shinsuke Harada, Akimasa Kinoshita
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Patent number: 9978840Abstract: In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.Type: GrantFiled: June 30, 2015Date of Patent: May 22, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hiromu Shiomi
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Patent number: 9954054Abstract: A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.Type: GrantFiled: June 30, 2015Date of Patent: April 24, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hiromu Shiomi
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Publication number: 20180040690Abstract: An active region through which current flows in a semiconductor device includes an n?-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n?-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n?-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n?-type layer and that of the n?-type silicon carbide epitaxial layer.Type: ApplicationFiled: August 4, 2017Publication date: February 8, 2018Applicants: FUJI ELECTRIC CO., LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yusuke KOBAYASHI, Hiromu SHIOMI, Shinya KYOGOKU, Shinsuke HARADA, Akimasa KINOSHITA
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Publication number: 20170141186Abstract: A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.Type: ApplicationFiled: June 30, 2015Publication date: May 18, 2017Inventor: Hiromu Shiomi
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Publication number: 20170133466Abstract: In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.Type: ApplicationFiled: June 30, 2015Publication date: May 11, 2017Applicant: Sumitomo Electric Industries, LtdInventor: Hiromu Shiomi
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Publication number: 20170133504Abstract: A step of forming a silicon carbide substrate includes steps of: forming a first impurity region having a first conductivity type by epitaxial growth; forming an embedded region by performing ion implantation into the first impurity region, the embedded region having a second conductivity type different from the first conductivity type, the embedded region being disposed cyclically; and forming a second impurity region by epitaxial growth, the second impurity region being in contact with the first impurity region and the embedded region, the second impurity region having the second conductivity type, the second impurity region having an impurity concentration lower than an impurity concentration of the embedded region. A trench is formed to have a side portion and a bottom portion. The trench is disposed at the same cycle as the embedded region.Type: ApplicationFiled: May 14, 2015Publication date: May 11, 2017Inventor: Hiromu SHIOMI
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Publication number: 20170110534Abstract: The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.Type: ApplicationFiled: May 14, 2015Publication date: April 20, 2017Inventor: Hiromu Shiomi