Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A control circuit causes a first cryptographic module to perform a dummy operation in a command processing period and a data processing period in which a second cryptographic module performs a normal operation while the first cryptographic module does not perform a normal operation.

Abstract: A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.

Abstract: A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.

Abstract: An object of the present invention is to provide a technique that makes it difficult to fabricate an illegal duplicate of a semiconductor storage apparatus. In a memory controller, an address acquisition unit acquires a latency-related designated address. The latency-related designated address is an address in the semiconductor memory storing data to be transmitted with the minimum latency upon reception of a read command, and is identical with an address held by a host. A pre-acquisition unit reads the data for the latency-related designated address from the semiconductor memory and stores it in the buffer. A comparator compares the address included in the read command to the latency-related designated address. Depending on the result of the comparison by the comparator, a transmission control unit transmits the data stored in the buffer to the host at the time point of completion of a minimum latency.