Patents by Inventor Hirono Tsubota

Hirono Tsubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microprocessor and data flow microprocessor having vector operation function
    Patent number: 5666535
    Abstract: A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: September 9, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Hirono Tsubota
  • Microprocessor and data flow microprocessor having vector operation function
    Patent number: 5404553
    Abstract: A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.
    Type: Grant
    Filed: January 2, 1992
    Date of Patent: April 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Hirono Tsubota
  • Data flow processor with data processing and next address determination being made in parallel
    Patent number: 5363491
    Abstract: A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: November 8, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Komori, Hirono Tsubota, Kenji Shima
  • Data flow processor with next destination node determination
    Patent number: 5218706
    Abstract: A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.
    Type: Grant
    Filed: December 13, 1989
    Date of Patent: June 8, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinji Komori, Hirono Tsubota, Kenji Shima