Abstract: A projector includes a projection lens and a projector body. In the projection lens, a U-shaped optical path is formed by optical axis to optical axis. A lens barrel is a U-shaped barrel. A housing of the projector body includes a storage section. The projection lens is supported rotatably about the optical axis with respect to the housing, in an up-down direction and a right-left direction of the housing perpendicular to the optical axis, between a first position where the projection lens is stored inside a storage section provided in the housing and a second position where the projection lens is protruding from the housing.

Abstract: A seat heater is installed between a seat pad that is a member supporting a load from a seated person sitting on a seat and has a plurality of ventilation holes through which the air generated by a blower flows is formed on a surface on a side of the seated person and a covering that covers a surface of the seat pad and has breathability. The seat heater includes a thin plate-like base material having voids through which air passes, and a heating wire fixed to the base material. A plurality of slits separate from the voids are formed in the base material.

Abstract: A display device includes: a base plate being provided on a first side of a display panel; a front-face supporting member facing the base plate with the display panel therebetween, having a periphery on an external side with respect to the display panel, and being joined to the base plate at part or all of a peripheral portion of the front-face supporting member; and a back-face supporting member facing the front-face supporting member with the base plate therebetween, and being joined to both of the front-face supporting member and the base plate at a peripheral portion of the back-face supporting member.

Abstract: A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

Abstract: A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.

Abstract: An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.

Abstract: An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.

Abstract: A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and a program counter control unit controlling a value of a program counter for providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during a consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced. This renders it possible to branch to an operation instruction executed during a consecutive execution and thus provide an enhanced efficiency of instruction-code compression.

Abstract: A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address in data memory is provided between the data memory and a data path unit. The alignment buffer outputs misaligned data by selecting misaligned data from data held in the register and data read from the data memory. The data held in the register is updated as word-aligned data is read out.

Abstract: A specific address region of a cache address region is set in a non-cache region setting register together with a region setting valid bit in a cache memory. When the specific address region is accessed by a CPU core, access to an external memory is made if a corresponding region is set in a non-cache region by a region setting valid bit. Moreover, an invalidating bit is set to invalidate all cache memory data in the specific address region. In DMA transfer, an inclusion detection circuit detects whether a transfer destination address region is included in the set address region and forcibly sets an invalidating bit according to a result of the detection. A cache system is provided that is capable of setting an address region of a cache object region according to a system architecture with flexibility.

Abstract: Read operation including misaligned data as operand data can be performed in a single cycle. An alignment buffer (6, 7) having a register to hold data stored at one address in data memory (4, 5) is provided between the data memory (4, 5) and a data path unit (3). The alignment buffer (6, 7) outputs misaligned data by selecting it from data held in the register and data read from the data memory (4, 5). The data held in the register is updated as word-aligned data is read out.

Abstract: A vibrator for a piezoelectric motor is produced by forming an elastic material into a predetermined shape, forming a piezoelectric material on the shaped elastic material for polarization and for driving, forming an electrode for polarization on the piezoelectric material, forming an electrode for driving on the surface of the electrode for polarization or on the piezoelectric material after stripping the electrode for polarization, and etching the elastic material into a predetermined shape has an elastic body and to remove the elastic body from a base. Instead of forming the piezoelectric material on the shaped elastic material for polarization and for driving, an electrode both for polarization and for driving can be formed on one face of the shaped elastic material, and the piezoelectric material can be formed on that electrode.

Abstract: Intermediate coupler for hoses attachable to a vehicle body including a fitment body with hose joints at opposite ends and a mounting bracket caulkedly bound to an intermediate base portion of the fitment body. The fitment body has, at the intermediate base portion in a consecutively stepped manner, a bracket mounting portion and a flange provided on one side of the bracket mounting portion. The flange has a diameter larger than that of the bracket mounting portion. The mounting bracket has an insert hole provided with a tapered surface divergent toward its outer end face.