Patents by Inventor Hironobu Miyamoto

Hironobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090173968
    Abstract: A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.
    Type: Application
    Filed: December 12, 2006
    Publication date: July 9, 2009
    Applicant: NEC CORPORATION
    Inventors: Kouji Matsunaga, Kazuki Ota, Yasuhiro Okamoto, Tatsuo Nakayama, Akio Wakejima, Yuji Ando, Hironobu Miyamoto, Takashi Inoue, Yasuhiro Murase
  • Publication number: 20090045438
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: October 25, 2006
    Publication date: February 19, 2009
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Publication number: 20090008678
    Abstract: An electron supply layer (13) is a layer which forms a heterojunction with a channel layer (12) and contains InzAlxGa1-zxN (0?z<1, 0<x<1, 0<x+z<1). On the electron supply layer (13), a gate electrode (17) is formed in contact with the electron supply layer (13). The Al composition ratio x1 at the interface between the electron supply layer (13) and the channel layer (12) and the Al composition ratio xa at the interface between the electron supply layer (13) and the gate electrode (17) satisfy the following conditions: x1/2?xa<x1 and x1?0.3.
    Type: Application
    Filed: January 29, 2007
    Publication date: January 8, 2009
    Applicant: NEC CORPORATION
    Inventors: Yuji Ando, Hironobu Miyamoto, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue
  • Patent number: 7459788
    Abstract: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: December 2, 2008
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20080179743
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 31, 2008
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7323783
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 29, 2008
    Assignee: NEC Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Publication number: 20080006853
    Abstract: The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 10, 2008
    Applicant: NEC CORPORATION
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando, Yasuhiro Okamoto, Masaaki Kuzuhara, Takashi Inoue, Koji Hataya
  • Patent number: 7256432
    Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: August 14, 2007
    Assignee: NEC Corporation
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Masaaki Kuzuhara
  • Publication number: 20070164326
    Abstract: A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode 1 and drain electrode 3, and SiON film 23 formed on electron supply layer 13. Gate electrode 2 has a field plate portion 5 that projects toward drain electrode 3 in the form of an eave on SiON film 23. The thickness of a portion (field plate layer 23a) of SiON film 23 lying between field plate portion 5 and electron supply layer 13 gradually increases from gate electrode 2 to drain electrode 3.
    Type: Application
    Filed: February 21, 2005
    Publication date: July 19, 2007
    Inventors: Yasuhiro Okamoto, Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Takashi Inque, Masaaki Kuzuhara
  • Publication number: 20070164305
    Abstract: An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.
    Type: Application
    Filed: February 28, 2005
    Publication date: July 19, 2007
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20070158692
    Abstract: The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side.
    Type: Application
    Filed: June 24, 2005
    Publication date: July 12, 2007
    Applicant: NEC CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Masaaki Kuzuhara, Yasuhiro Okamoto, Takashi Inoue, Koji Hataya
  • Publication number: 20070018316
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Application
    Filed: December 6, 2004
    Publication date: January 25, 2007
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7071526
    Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: July 4, 2006
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Yasuhiro Okamoto, Kensuke Kasahara, Tatsuo Nakayama, Masaaki Kuzuhara
  • Publication number: 20060102929
    Abstract: A field plate portion (5) overhanging a drain side in a visored shape is formed in a gate electrode (2). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed beneath the field plate portion (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered therewith.
    Type: Application
    Filed: December 15, 2003
    Publication date: May 18, 2006
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Massaki Kuzuhara
  • Publication number: 20060054929
    Abstract: A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
    Type: Application
    Filed: November 29, 2004
    Publication date: March 16, 2006
    Inventors: Tatsuo Nakayama, Yuji Ando, Hironobu Miyamoto, Kensuke Kasahara, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Publication number: 20060043415
    Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).
    Type: Application
    Filed: December 15, 2003
    Publication date: March 2, 2006
    Applicant: NEC Corporation
    Inventors: Yasuhiro Okamoto, Hironobu Miyamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Masaaki Kuzuhara
  • Publication number: 20050151255
    Abstract: A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed.
    Type: Application
    Filed: June 17, 2003
    Publication date: July 14, 2005
    Inventors: Yuji Ando, Hironobu Miyamoto, Yasuhiro Okamoto, Kensuke Kasahara, Tatsuo Nakayama, Masaaki Kuzuhara
  • Patent number: 6765241
    Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: July 20, 2004
    Assignee: NEC Corporation
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Publication number: 20030151064
    Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, the heat diffusion characteristic and the device performance in high-speed operation, and, therefor, in a group III nitride semiconductor device of the present invention, an epitaxial growth layer 13 of a group III nitride semiconductor with a buffer layer 12 laid under it is formed on a sapphire substrate 11 in which an A plane (an (11-20) plane) is set to be the principal plane, and thereon a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed, wherein a thickness of the single crystalline sapphire substrate is specifically set to be 100 &mgr;m or less.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 14, 2003
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Patent number: 6552373
    Abstract: A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 22, 2003
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Naotaka Iwata, Koji Matsunaga, Masaaki Kuzuhara, Kensuke Kasahara, Kazuaki Kunihiro, Yuji Takahashi, Tatsuo Nakayama, Nobuyuki Hayama, Yasuo Ohno