Abstract: Electrode lead terminals in a number not less than three are attached to a cathode foil and an anode foil. The electrode lead terminals include at least one cathode lead terminal attached to the cathode foil and at least one anode lead terminal attached to the anode foil. A winding core having an axis is prepared. The cathode foil and the anode foil are wound around the winding core, being overlapped each other. A cross section of the winding core perpendicular to the axis includes an outer edge having a portion along each side of a polygon with the above number of sides. Thereby, a method for manufacturing an electrolytic capacitor capable of suppressing displacement of a lead terminal can be provided.

Abstract: Electrode lead terminals in a number not less than three are attached to a cathode foil and an anode foil. The electrode lead terminals include at least one cathode lead terminal attached to the cathode foil and at least one anode lead terminal attached to the anode foil. A winding core having an axis is prepared. The cathode foil and the anode foil are wound around the winding core, being overlapped each other. A cross section of the winding core perpendicular to the axis includes an outer edge having a portion along each side of a polygon with the above number of sides. Thereby, a method for manufacturing an electrolytic capacitor capable of suppressing displacement of a lead terminal can be provided.

Abstract: A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.

Abstract: An object of the present invention is to provide an optical film, a light diffusion film and supports thereof exhibiting reduced film deformation in the case of the storage at high-temperature and humidity as well as excellent heat resistance, accompanied with no generation of scratches on the film surface, film peeling and curl.

Abstract: A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.

Abstract: A method of producing a semiconductor memory device forms an overlap between a distribution of semiconductor clusters in a gate insulating layer and a drain region by oblique ion implantation using the edge of the semiconductor cluster distribution as a self-align mask. At least a portion of the semiconductor cluster distribution which is the nearest to the Si substrate and the drain overlaps a drain diffusion layer, and the semiconductor clusters are overlapped with each other. Thus, the device has a 1Tr/cell structure. As a result, the properties of a nonvolatile memory device using an insulating film are improved.

Abstract: The present invention provides a nonvolatile semiconductor memory which has advantages permitting the cell of the memory circuit to integrate, the memory circuit to be easy to manufacture, and the manufacturing expense to be cut down. The nonvolatile memory 21 comprises a P type well for which a N+ type source 4 and a N+ type drain 3 are provided. A surface of a space between the source 4 and the drain 3 comprises a first portion 10a and a second portion 10b. An insulating layer 6 for holding electrons spans the surface of the space. A memory gate electrode 5 is on the insulating layer 6 and spans the first portion 10a. An insulating body 23 is formed on the surface of the insulating layer 6 so that it connects to the memory gate electrode 5 through an insulating layer 8 and spans the second portion 10b.

Abstract: A semiconductor nonvolatile memory comprised of a p-type silicon substrate 3, an n.sup.+ drain 5 and an n.sup.+ source 9, the source and the drain regions defining an MOS channel region 7. On top of the channel region 7 there are laminated a silicon dioxide film 18 and a semiconductor rich oxide film 20 which has been nitrided so as to leave silicon nitride region therein. Further on top of these layers, there is formed a polysilicon film 22, which is etched to form a control electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory (EPROM) is constructed.

Abstract: In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.

Abstract: When a semiconductor is manufactured by a resist mask process while using photolithography techniques, the gate wiring width is increased without increasing the cell area by providing a sidewall on the gate mask and using the sidewall as a mask. The sidewall is produced by applying a CVD oxide film to the mask and removing the oxide film by anisotropic etching. This provides a minimum gate line width of 0.7.mu. and a minimum space width of 0.3.mu..

Abstract: Two memory cells are formed adjacent each other on a semiconductor substrate. In each memory cell, eight MOS transistors are formed between two selection transistors such that the MOS transistors and the selection transistors are connected in series, and that a source/drain diffusion layer is shared by adjacent ones of the selection transistors and the MOS transistors. A drain layer is shared by two adjacent selection transistors of the two memory cells. Ferroelectric capacitors are formed on the respective MOS transistors. A common electrode serves both as a gate electrode of the MOS transistor and a bottom electrode of the ferroelectric capacitor. Gate electrodes of the selection transistors, the common electrodes, and top electrodes of the ferroelectric capacitors are connected to word lines, and the above drain diffusion layer is connected to a bit line.

Abstract: A high dielectric film instead of an oxidizing film conventionally used is used in the non-volatile memory of an MoNoS construction. Using a mixed film composed of a high dielectric constant film and an amorphous insulating film for the trap film, the ratio of the voltage applied to the tunnel oxidizing film is increased so that writing and erasing operations can be effected with a low voltage. Penetration of the electrons into the electrode and the flow of positive holes from the electrode are prevented so as to increase the flow efficiency.

Abstract: The present invention provides nonvolatile semiconductor memory which has advantages permitting the cell of the memory circuit to integrate, the memory circuit to be easy to manufacture, and the manufacturing expense to be cut down. The nonvolatile memory (21) comprises a P type well for which a N+ type source (4) and a N+ type drain (3) is provided. A surface of a space between the source (4) and the drain (3) comprises a first portion (10a) and a second portion (10b). An insulating layer (6) for holding electrons spans the surface of the space. A memory gate electrode (5) is on the insulating layer (6) and spans the first portion (10a). The surface of the second portion (10b) and a part of the surface of the memory gate electrode (5) is covered with a first region electrode (24) attaching to the source (4). But the first region electrode (24) is insulated from the memory gate electrode (5) with the insulating layer (8).

Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.

Abstract: A non-volatile storage device such as a PROM (Programmable Read Only Memory). To obtain an adequate sum of captured charges by a low storing voltage and to prevent charges from being injected from a gate electrode, a silicon oxide film, a composite silicon oxide/nitride film and a silicon oxide film are formed in order on a gate region of a silicon substrate on which a source region and a drain region are formed. Since the composite silicon oxide/nitride film has many interfaces between the silicon oxide region and the silicon nitride region, it accumulates a lot of charges from the silicon substrates.

Abstract: Two memory cells are formed adjacent each other on a semiconductor substrate. In each memory cell, eight MOS transistors are formed between two selection transistors such that the MOS transistors and the selection transistors are connected in series, and that a source/drain diffusion layer is shared by adjacent ones of the selection transistors and the MOS transistors. A drain layer is shared by two adjacent selection transistors of the two memory cells. Ferroelectric capacitors are formed on the respective MOS transistors. A common electrode serves both as a gate electrode of the MOS transistor and a bottom electrode of the ferroelectric capacitor. Gate electrodes of the selection transistors, the common electrodes, and top electrodes of the ferroelectric capacitors are connected to word lines, and the above drain diffusion layer is connected to a bit line.

Abstract: In an element forming region isolated from other regions by a field oxide, one select transistor and a plurality of MOS transistors are connected in series so that a source/drain diffusion region is commonly owned by two neighboring transistors. The gate electrodes of the MOS transistors are connected to the lower electrodes of ferroelectric capacitors, respectively. The gate electrode of the select transistor, and the lower electrodes and upper electrodes of the ferroelectric capacitors are led out as word lines. A metal wiring which serves as a bit line is connected to a drain diffusion region.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A non-volatile storage device such as an EPROM (erasable programmable read only memory) and a method of manufacturing the same. A silicon oxide film, a silicon nitride film and a silicon oxide film are formed one after another on a gate region of a semiconductor substrate in which a source region and a drain region are formed. To restrict carrier capture to the silicon nitride film near the source region, impurity ions such as hydrogen ions are mixed with the silicon nitride film at a side toward the source region.

Abstract: Si regions separated from a Si-rich SiO.sub.2 film are nitrided to provide a film mainly consisting of SiO.sub.2 regions an Si.sub.3 N.sub.4 regions to be used for constituting a dielectric device or a capacitor.