Abstract: A scan test apparatus for operating a test unit according to a test pattern and outputs address information of the test pattern at which a fail takes place, which includes a memory unit for holding circuit information in which scan flip-flops are written at corresponding addresses and a control unit for outputting, in addition to the address information, a scan flip-flop name from the memory unit corresponding to the address information.

Abstract: The present invention is to provide an IC fault location tracing apparatus with which a user having any knowledge of the DUT design is easily able to identify the IC fault location in a short period of time.

Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is process performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in thee specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.

Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.

Abstract: An IC fault analysis system which is capable of accurately correlating mask layout data and/or net listing data associated with CAD (computer aided design) data developed in the IC design and an image obtained by a non-contact type tester such as an electron beam tester.

Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.

Abstract: The present invention allows to automatically presume a defect location of an IC using an EB tester. Under each of the conditions where a normal power supply voltage and an abnormal power supply voltage are applied to an IC respectively, test patterns are applied to the IC until the pattern address where the first defect is detected by an IC tester. At this point in time, the pattern update is stopped. Then a potential contrast image data is acquired from one of the partitioned segments of the IC surface for each of the above power supply conditions. A diffrence image data between the two potential contrast image data (normal power case and abnormal power case) is generated. This difference image data generation is repeated several times and those defference image data are summed up. A check is made to see if there is a changed portion greater than a predetermined value in each of the segments and if there is, a defect information is stored in a storage portion corresponding to the defect segment.

Abstract: In a D/A converting apparatus which provides a converted analog signal at its output terminal by selectively yielding one or more currents from one or more current sources in accordance with an input digital signal, the current sources are selectively actuated to output the currents and an error in the current of each selected current source is obtained from the output derived at the output terminal in response to the outputting of the current. From the current error of each current source is computed a final error corresponding to each input digital signal and corrected data corresponding to the final error is stored in a corrected data memory, which is read out by the input digital signal. The output thus read out is converted into an analog signal, whereby a correct converted output is obtained.

Abstract: A method and apparatus for drawing, by an electron beam, patterns on a semiconductor wafer for fabricating of an integrated circuit. Chip areas on the semiconductor wafer are each divided into rectangular blocks arrayed in rows and columns. The deflection field of the electron beam is selected slightly larger than each block. Real block marks, indicating the positions of respective blocks, are provided on every side of the chip area. The specimen is fed so that a block array starting at one corner of the chip area passes through the deflection field along one side of the array. Upon detecting the block marks at three corners of a first block of the array, correction coefficients for the block are computed based on the positions of the three detected real block marks and then an imaginary block mark is set at the remaining corner of the block on the basis of the correction coefficients.