Patents by Inventor Hironobu Oura

Hironobu Oura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipeline testing method, pipeline testing system, pipeline test instruction generation method and storage method
    Patent number: 6732297
    Abstract: This invention relates to a method of generating a test-instruction string to test the pipeline mechanism of a processor, which automatically generates from randomly generated instructions an instruction string which causes a pipeline interlock. This invention comprises a table for notifying the subsequent instruction of the status of resource usage of the leading instruction and, by generating the resources used, by the subsequent instruction according to the status of resource usage of the table automatically generates a subsequent instruction that interferes with the leading instruction.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 4, 2004
    Assignee: Fujitsu Limited
    Inventor: Hironobu Oura
  • Method and apparatus for testing a cache
    Patent number: 6701461
    Abstract: By disposing a cache registration table (23) for managing the situation of use of each block in the cache to be tested in a cache testing command row creating device (10), for testing the cache in an apparatus to be tested (31), a plurality of testing commands (memory access commands) can be created in which memory access addresses are set randomly and the block to be accessed are set without duplication, so that testing commands not changing in the access priority rank, if cache hit may occur, may be prepared.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: March 2, 2004
    Assignee: Fujitsu Limited
    Inventor: Hironobu Oura
  • Pipeline testing method, pipeline testing system, pipeline test instruction generation method and storage medium
    Publication number: 20010014957
    Abstract: This invention relates to a method for generating a test-instruction string for testing the pipeline mechanism of a processor, and which automatically generates from randomly generated instructions and instruction string which causes a pipeline interlock. This invention comprises a table (50 to 53) for notifying the subsequent instruction of the status of resource usage of the leading instruction, and by generating the resources used by the subsequent instruction according to the status of resource usage of the table (50 to 53), automatically generates a subsequent instruction that interferes with the leading instruction.
    Type: Application
    Filed: November 30, 2000
    Publication date: August 16, 2001
    Inventor: Hironobu Oura
  • Method and apparatus for testing a cache
    Publication number: 20010001157
    Abstract: By disposing a cache registration table (23) for managing the situation of use of each block in the cache to be tested in a cache testing command row creating device (10), for testing the cache in an apparatus to be tested (31), a plurality of testing commands (memory access commands) can be created in which memory access addresses are set randomly and the block to be accessed are set without duplication, so that testing commands not changing in the access priority rank, if cache hit may occur, may be prepared.
    Type: Application
    Filed: December 18, 2000
    Publication date: May 10, 2001
    Inventor: Hironobu Oura