Patents by Inventor Hironobu Sakata

Hironobu Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220253332
    Abstract: An operation automation system includes an input/output device inputting information for specifying a component of a relation display target in a data processing flow in which a plurality of hierarchies respectively including at least one component are hierarchically configured; and a processor that selects a display mode for performing normal display for a first hierarchy to which the component of the relation display target belongs, selects a display mode for performing simple display for a second hierarchy to which a component including a hierarchy to which the component of the relation display target belongs, and selects a display mode for performing non-display for a third hierarchy but neither the first hierarchy nor the second hierarchy to which the component including the hierarchy to which the component of the relation display target belongs, in the plurality of hierarchies configuring the data processing flow.
    Type: Application
    Filed: September 7, 2021
    Publication date: August 11, 2022
    Inventors: Kensuke IKEMOTO, Tadashi YAGAME, Hironobu SAKATA
  • Publication number: 20210158248
    Abstract: A computer system includes a business system operating services each providing a function corresponding to a request. the computer system comprises: a controller generating a schedule for changing an allocation amount of a resource of the business system for a service; and an allocation change unit changing the allocation amount of the resource for the service based on the schedule. The controller calculates in a case of detecting reception of a request for starting processing, a reception count of the detected request; identifies related services; calculate a predicted value of an index indicating a load of each of the related services based on the reception count of the request; determines whether it is necessary to change the allocation amount of the resource for the each of the related services; and generates the schedule of a determined related service.
    Type: Application
    Filed: August 31, 2020
    Publication date: May 27, 2021
    Inventors: Ryo UENISHI, Takaki KURODA, Hiroshi HAYAKAWA, Masashi YAKU, Hironobu SAKATA
  • Publication number: 20200394091
    Abstract: A failure analysis support system calculates a failure analysis period based on a metric performance value of a bottleneck candidate resource and a metric base value corresponding to the metric performance value, identifies a bottleneck candidate related resource related to the bottleneck candidate resource by referring to inter-resource relation information, calculates an evaluation value of the bottleneck candidate related resource based on a metric performance value of the bottleneck candidate related resource and a metric base value corresponding to the metric performance value, identifies a to-be-displayed bottleneck candidate related resource from the bottleneck candidate related resource based on the evaluation value, and displays a mutual relationship between display resources including a base point resource, a base point-related resource, the bottleneck candidate resource, and the to-be-displayed bottleneck candidate related resource, and a status of the display resources at each time point in the fa
    Type: Application
    Filed: March 10, 2020
    Publication date: December 17, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Arata KOKUBUN, Yusuke ASAI, Takaki KURODA, Masashi YAKU, Hironobu SAKATA, Taiki EIRAKU, Hidenobu MURAMATSU
  • Patent number: 10282095
    Abstract: Proposed are a method and a device for managing the performance of a storage apparatus which uses a combination of different types of drive devices which mutually have different limits as its storage medium so that measures can be systematically taken against problems that may arise in the future as a result of the drive devices reaching their limit. Based on a premise of being able to tier two or more types of storage mediums which have mutually different rewriting limits and response performances and migrate data between the respective tiers according to the response performance, a performance management device estimates a decrement of a storage capacity pursuant to each of the two or more types of storage mediums reaching a rewriting limit, estimates a performance influence on the virtual volume and a timing of occurrence, and displays information related to the estimated performance influence and the timing of occurrence.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 7, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kazuya Sato, Hideo Ohata, Hironobu Sakata, Katsutaka Inoue
  • Publication number: 20180210656
    Abstract: Proposed are a method and a device for managing the performance of a storage apparatus which uses a combination of different types of drive devices which mutually have different limits as its storage medium so that measures can be systematically taken against problems that may arise in the future as a result of the drive devices reaching their limit. Based on a premise of being able to tier two or more types of storage mediums which have mutually different rewriting limits and response performances and migrate data between the respective tiers according to the response performance, a performance management device estimates a decrement of a storage capacity pursuant to each of the two or more types of storage mediums reaching a rewriting limit, estimates a performance influence on the virtual volume and a timing of occurrence, and displays information related to the estimated performance influence and the timing of occurrence.
    Type: Application
    Filed: March 9, 2016
    Publication date: July 26, 2018
    Applicant: HITACHI, LTD.
    Inventors: Kazuya SATO, Hideo OHATA, Hironobu SAKATA, Katsutaka INOUE
  • Patent number: 9626110
    Abstract: Multiple storage apparatuses each provide a virtual logical volume composed of multiple logical pages to a host computer. A management computer determines a target logical page to which data are migrated to achieve a volume goal performance on the basis of access path information that can identify a storage apparatus that receives an I/O request in which the virtual logical volume is specified, an actual volume response performance, the volume goal performance to be attained, a page response performance of the logical page, and storage destination information that can identify a storage apparatus in which a storage area allocated to the logical page is present, and migrates data of the logical page between storage apparatuses.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 18, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hironobu Sakata, Hideo Ohata, Naoshi Maniwa
  • Publication number: 20150248245
    Abstract: Multiple storage apparatuses each provide a virtual logical volume composed of multiple logical pages to a host computer. A management computer determines a target logical page to which data are migrated to achieve a volume goal performance on the basis of access path information that can identify a storage apparatus that receives an I/O request in which the virtual logical volume is specified, an actual volume response performance, the volume goal performance to be attained, a page response performance of the logical page, and storage destination information that can identify a storage apparatus in which a storage area allocated to the logical page is present, and migrates data of the logical page between storage apparatuses.
    Type: Application
    Filed: February 22, 2013
    Publication date: September 3, 2015
    Inventors: Hironobu Sakata, Hideo Ohata, Naoshi Maniwa
  • Patent number: 4757442
    Abstract: A multi-processing device includes three or more processing systems, each having a processor and a corresponding main memory connected to each other by means of an individual memory bus. The multi-processing device also includes a common memory bus connectable to all the processors and all the main memories of the respective systems, an asynchronism detection circuit connected to the respective processors to produce an asynchronism detection signal indicating which system or systems are in asynchronous state, and a device control circuit responsive to the asynchronism detection signal to send a common memory bus select signal to the main memory of each failed system to change its bus connection from the individual memory bus to the common memory bus. The device control circuit also generates a master designation signal for allowing an arbitrary processor of the normal non-faulty systems to be designated as a master processor, and a copy request signal to the respective processors.
    Type: Grant
    Filed: June 16, 1986
    Date of Patent: July 12, 1988
    Assignee: NEC Corporation
    Inventor: Hironobu Sakata