Patents by Inventor Hironori Inoue
Hironori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142482Abstract: Disclosed is a specimen measurement apparatus comprising: a measurement unit configured to suction a specimen from a specimen container and measure the suctioned specimen; and a specimen transport unit configured to transport the specimen container to the measurement unit, wherein the specimen transport unit includes a rack setting part configured to allow a specimen rack to be set thereon, the specimen rack holding the specimen container that has not been subjected to specimen suction by the measurement unit, a rack collection part configured to collect the specimen rack holding the specimen container that has been subjected to specimen suction by the measurement unit, and an interruption specimen setting part configured to allow the specimen rack to be set thereon, the specimen rack holding the specimen container that is to be subjected to specimen suction by the measurement unit in preference to the specimen container held by the specimen rack having been set on the rack setting part, and the interruptionType: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Applicant: Sysmex CorporationInventors: Masashi Tada, Taku INOUE, Hironori Katsumi, Takaaki Nagai
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Publication number: 20240142483Abstract: Disclosed is a specimen measurement apparatus comprising: a measurement unit configured to suction a specimen from a specimen container and measure the suctioned specimen; and a specimen transport unit configured to transport the specimen container to the measurement unit, wherein the specimen transport unit includes a first transport part including a first placement surface configured to allow a specimen rack to be placed thereon, the first transport part being configured to transport a plurality of the specimen racks, each holding the specimen container, on the first placement surface, and a second transport part disposed above the first transport part and including a second placement surface configured to allow the specimen rack to be placed thereon, the second transport part being configured to transport a plurality of the specimen racks on the second placement surface, and at least one of the first transport part and the second transport part is configured to allow the specimen rack to be taken out thereType: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Applicant: Sysmex CorporationInventors: Masashi Tada, Taku INOUE, Hironori KATSUMI
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Patent number: 10708535Abstract: There is provided a light output system (100) including a speaker (170), a light output unit (135, 130), and a processor 110 to cause first audio and second audio to be output from the speaker (170) and cause the light output unit (135, 130) to output light corresponding to the second audio output.Type: GrantFiled: March 9, 2017Date of Patent: July 7, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroki Abe, Hideki Nishimura, Shusaku Mizukami, Hironori Inoue
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Publication number: 20190199958Abstract: There is provided a light output system (100) including a speaker (170), a light output unit (135, 130), and a processor 110 to cause first audio and second audio to be output from the speaker (170) and cause the light output unit (135, 130) to output light corresponding to the second audio output.Type: ApplicationFiled: March 9, 2017Publication date: June 27, 2019Inventors: HIROKI ABE, HIDEKI NISHIMURA, SHUSAKU MIZUKAMI, HIRONORI INOUE
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Patent number: 9348628Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: GrantFiled: March 18, 2013Date of Patent: May 24, 2016Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Patent number: 9189070Abstract: In a content display device (1) of the present invention, a scrolling processing section (107) causes a scrolling movement of a currently-displayed shelf face (11) in a lengthwise direction to be displayed in a case where a second input operation instructing display of the currently-displayed shelf face (11) in a different position in the lengthwise direction is carried out via an input operation section (111). A rotation processing section (106) causes rotation of a bookshelf object (10) on a central axis of the bookshelf object (10) to be displayed in a case where a first input operation instructing display of a shelf face (11) different from the currently-displayed shelf face (11) is carried out via the input operation section (111).Type: GrantFiled: September 21, 2011Date of Patent: November 17, 2015Assignee: Sharp Kabushiki KaishaInventors: Sunao Yamaguchi, Shinichiro Ota, Yu Matsumoto, Hironori Inoue, Masayuki Nakazawa, Toshiroh Mukai
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Patent number: 9189293Abstract: Computer including a plurality of physical CPUs, a plurality of virtual computers which execute predetermined processing and to which one of the plurality of physical CPUs is assigned, and a virtual computer control component able to cause the plurality of physical CPUs to execute overhead processing required by plurality of virtual computers. Virtual computer control component configured to: (A) upon causing the physical CPU, in which processing of the virtual computer is in a running state, to execute overhead processing, measure a run time used by the physical CPU to manage a cumulative run time, for each of the physical CPUs; and (B) upon causing the overhead processing to be executed subsequent to the (A), select a physical CPU in which the cumulative run time is smallest as the physical CPU to execute the overhead processing.Type: GrantFiled: June 3, 2013Date of Patent: November 17, 2015Assignee: Hitachi, Ltd.Inventors: Hironori Inoue, Shuhei Matsumoto
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Publication number: 20150128184Abstract: A display control section (220c) of a television (1) causes a display unit (205) to simultaneously display (i) a recommended content panel (122a) corresponding to a recommended content extracted from a population consisting of programs on different channels in the same time slot and (ii) a recommended content panel (122b) corresponding to a recommended content extracted from a population consisting of future programs. This reduces a user's troublesome operation.Type: ApplicationFiled: March 14, 2013Publication date: May 7, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiro Tai, Hideki Nishimura, Hironori Inoue, Nobuko Miura, Yosuke Iga
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Publication number: 20150074603Abstract: A focus frame (500) (i) is provided on a menu screen (410) on which a number of menu items to be selected (121a, 121b, 121c, 122a, and 122b) and the like are displayed and (ii) is located around a specific menu item to be selected (121a). A mark, such as an arrow, indicating a direction in which a menu item is selectable is put close to each of an upper side, a lower side, a right side, and a left side of the focus frame (500) so that a viewer can easily select a target menu item in accordance with an instruction indicated by the mark.Type: ApplicationFiled: March 27, 2013Publication date: March 12, 2015Applicant: Sharp Kabushiki KaishaInventors: Hiroki Abe, Hironori Inoue, Masao Kurino, Yosuke Iga, Takamasa Shimizu
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Patent number: 8898675Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.Type: GrantFiled: December 6, 2011Date of Patent: November 25, 2014Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Patent number: 8695007Abstract: A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.Type: GrantFiled: March 4, 2011Date of Patent: April 8, 2014Assignee: Hitachi, Ltd.Inventors: Shintaro Wada, Shuhei Matsumoto, Hironori Inoue, Kenichiro Yamato
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Publication number: 20130347000Abstract: Computer including a plurality of physical CPUs, a plurality of virtual computers which execute predetermined processing and to which one of the plurality of physical CPUs is assigned, and a virtual computer control component able to cause the plurality of physical CPUs to execute overhead processing required by plurality of virtual computers. Virtual computer control component configured to: (A) upon causing the physical CPU, in which processing of the virtual computer is in a running state, to execute overhead processing, measure a run time used by the physical CPU to manage a cumulative run time, for each of the physical CPUs; and (B) upon causing the overhead processing to be executed subsequent to the (A), select a physical CPU in which the cumulative run time is smallest as the physical CPU to execute the overhead processing.Type: ApplicationFiled: June 3, 2013Publication date: December 26, 2013Inventors: Hironori INOUE, Shuhei MATSUMOTO
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Publication number: 20130159936Abstract: In a content display device (1) of the present invention, a scrolling processing section (107) causes a scrolling movement of a currently-displayed shelf face (11) in a lengthwise direction to be displayed in a case where a second input operation instructing display of the currently-displayed shelf face (11) in a different position in the lengthwise direction is carried out via an input operation section (111). A rotation processing section (106) causes rotation of a bookshelf object (10) on a central axis of the bookshelf object (10) to be displayed in a case where a first input operation instructing display of a shelf face (11) different from the currently-displayed shelf face (11) is carried out via the input operation section (111).Type: ApplicationFiled: September 21, 2011Publication date: June 20, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Sunao Yamaguchi, Shinichiro Ota, Yu Matsumoto, Hironori Inoue, Masayuki Nakazawa, Toshiroh Mukai
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Patent number: 8464258Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.Type: GrantFiled: April 26, 2011Date of Patent: June 11, 2013Assignee: Hitachi, Ltd.Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue
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Patent number: 8423999Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: GrantFiled: July 12, 2010Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Patent number: 8266629Abstract: Attempts are made to reduce the system overhead generated at the time of context save/restore processing to perform process switching in a virtual machine system. In a CPU occupancy mode that a physical CPU is exclusively allocated to virtual machines, a logical CPU process running on the physical CPU is static, so that it is not necessary to save/restore the context every time the processes are switched. When a switching source process is a logical CPU process in a CPU occupancy mode, a context save is temporarily suspended. When switching to the same logical CPU process is made again continuously, save/restore is skipped. When the logical CPU process of a VMM control VM runs in that period, the logical CPU process whose save is delayed is recorded and saved late.Type: GrantFiled: December 1, 2009Date of Patent: September 11, 2012Assignee: Hitachi, Ltd.Inventors: Hironori Inoue, Shuhei Matsumoto
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Publication number: 20120174114Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.Type: ApplicationFiled: December 6, 2011Publication date: July 5, 2012Inventors: SHUHEI MATSUMOTO, Hironori Inoue, Shintaro Wada
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Publication number: 20110302579Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.Type: ApplicationFiled: April 26, 2011Publication date: December 8, 2011Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue
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Publication number: 20110225591Abstract: A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.Type: ApplicationFiled: March 4, 2011Publication date: September 15, 2011Inventors: SHINTARO WADA, Shuhei Matsumoto, Hironori Inoue, Kenichiro Yamato
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Publication number: 20110010713Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: ApplicationFiled: July 12, 2010Publication date: January 13, 2011Applicant: HITACHI, LTD.Inventors: Shuhei MATSUMOTO, Hironori INOUE, Shintaro WADA