Patents by Inventor Hironori Inoue

Hironori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240300538
    Abstract: A vehicle control device includes one or more processors configured to: on a travel route of an autonomous driving taxi configured to travel toward a desired drop-off position of a user of the autonomous driving taxi, set a predetermined travel route range from a point behind the desired drop-off position to the desired drop-off position, as a permissible midway drop-off range in which midway drop-off from the autonomous driving taxi is permitted; receive a setting about a midway drop-off position in the permissible midway drop-off range, the setting being made by the user in the autonomous driving taxi configured to travel toward the desired drop-off position; and stop the autonomous driving taxi at the midway drop-off position set by the user such that the user drops off the autonomous driving taxi midway.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 12, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naotoshi KADOTANI, Yuki NISHIKAWA, Yuki TAKAHASHI, Nana KIKUIRE, Takahiko KUWABARA, Ryusei GICHU, Takashi OTA, Toshifumi IWASE, Hironori ITO, Hisanobu INOUE
  • Publication number: 20240302177
    Abstract: An information processing device includes one or more processors configured to: set, as a travel destination of a vehicle, a point where an occupant of the vehicle gets out of the vehicle to transfer from the vehicle to a regularly operated transportation facility; acquire delay information indicating occurrence of a delay of the regularly operated transportation facility or occurrence of an event that causes a delay in travel of the vehicle to the travel destination; and change the travel destination of the vehicle based on the delay information.
    Type: Application
    Filed: February 28, 2024
    Publication date: September 12, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naotoshi KADOTANI, Yuki NISHIKAWA, Yuki TAKAHASHI, Nana KIKUIRE, Takahiko KUWABARA, Ryusei GICHU, Takashi OTA, Toshifumi IWASE, Hironori ITO, Hisanobu INOUE
  • Publication number: 20240265807
    Abstract: An information processing device includes a movement route receiving unit, an operation-related information acquiring unit, and a display control unit. The movement route receiving unit configured to receive, from an outside, a movement route of a passenger of a vehicle that includes transfer from the vehicle to a scheduled transportation system. The operation-related information acquiring unit configured to acquire operation-related information of the scheduled transportation system to which the passenger is expected to transfer. The display control unit configured to display the operation-related information on a display screen disposed in a cabin of the vehicle.
    Type: Application
    Filed: December 11, 2023
    Publication date: August 8, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naotoshi KADOTANI, Yuki NISHIKAWA, Yuki TAKAHASHI, Nana KIKUIRE, Takahiko KUWABARA, Ryusei GICHU, Takashi OTA, Toshifumi IWASE, Hironori ITO, Hisanobu INOUE
  • Publication number: 20240245138
    Abstract: Provided is a flavor inhalation instrument or the like that is controlled on the basis of motion of said flavor inhalation instrument or the like. A device, which is a flavor inhalation instrument or an aerosol generation device, comprises: a vibrator, a sensor which is configured to detect the motion of the device; a conversion unit which is configured to convert input data representing the detected motion into vibration data for vibrating the vibrator; and a control unit which is configured to vibrate the vibrator on the basis of the vibration data.
    Type: Application
    Filed: April 8, 2024
    Publication date: July 25, 2024
    Applicant: Japan Tobacco Inc.
    Inventors: Takuya SHIRAISHI, Ayumi GOTO, Hironori SATOMURA, Jumpei INOUE
  • Patent number: 10708535
    Abstract: There is provided a light output system (100) including a speaker (170), a light output unit (135, 130), and a processor 110 to cause first audio and second audio to be output from the speaker (170) and cause the light output unit (135, 130) to output light corresponding to the second audio output.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Abe, Hideki Nishimura, Shusaku Mizukami, Hironori Inoue
  • Publication number: 20190199958
    Abstract: There is provided a light output system (100) including a speaker (170), a light output unit (135, 130), and a processor 110 to cause first audio and second audio to be output from the speaker (170) and cause the light output unit (135, 130) to output light corresponding to the second audio output.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 27, 2019
    Inventors: HIROKI ABE, HIDEKI NISHIMURA, SHUSAKU MIZUKAMI, HIRONORI INOUE
  • Patent number: 9348628
    Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 24, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
  • Patent number: 9189293
    Abstract: Computer including a plurality of physical CPUs, a plurality of virtual computers which execute predetermined processing and to which one of the plurality of physical CPUs is assigned, and a virtual computer control component able to cause the plurality of physical CPUs to execute overhead processing required by plurality of virtual computers. Virtual computer control component configured to: (A) upon causing the physical CPU, in which processing of the virtual computer is in a running state, to execute overhead processing, measure a run time used by the physical CPU to manage a cumulative run time, for each of the physical CPUs; and (B) upon causing the overhead processing to be executed subsequent to the (A), select a physical CPU in which the cumulative run time is smallest as the physical CPU to execute the overhead processing.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: November 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Inoue, Shuhei Matsumoto
  • Patent number: 9189070
    Abstract: In a content display device (1) of the present invention, a scrolling processing section (107) causes a scrolling movement of a currently-displayed shelf face (11) in a lengthwise direction to be displayed in a case where a second input operation instructing display of the currently-displayed shelf face (11) in a different position in the lengthwise direction is carried out via an input operation section (111). A rotation processing section (106) causes rotation of a bookshelf object (10) on a central axis of the bookshelf object (10) to be displayed in a case where a first input operation instructing display of a shelf face (11) different from the currently-displayed shelf face (11) is carried out via the input operation section (111).
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 17, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Sunao Yamaguchi, Shinichiro Ota, Yu Matsumoto, Hironori Inoue, Masayuki Nakazawa, Toshiroh Mukai
  • Publication number: 20150128184
    Abstract: A display control section (220c) of a television (1) causes a display unit (205) to simultaneously display (i) a recommended content panel (122a) corresponding to a recommended content extracted from a population consisting of programs on different channels in the same time slot and (ii) a recommended content panel (122b) corresponding to a recommended content extracted from a population consisting of future programs. This reduces a user's troublesome operation.
    Type: Application
    Filed: March 14, 2013
    Publication date: May 7, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Tai, Hideki Nishimura, Hironori Inoue, Nobuko Miura, Yosuke Iga
  • Publication number: 20150074603
    Abstract: A focus frame (500) (i) is provided on a menu screen (410) on which a number of menu items to be selected (121a, 121b, 121c, 122a, and 122b) and the like are displayed and (ii) is located around a specific menu item to be selected (121a). A mark, such as an arrow, indicating a direction in which a menu item is selectable is put close to each of an upper side, a lower side, a right side, and a left side of the focus frame (500) so that a viewer can easily select a target menu item in accordance with an instruction indicated by the mark.
    Type: Application
    Filed: March 27, 2013
    Publication date: March 12, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroki Abe, Hironori Inoue, Masao Kurino, Yosuke Iga, Takamasa Shimizu
  • Patent number: 8898675
    Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
  • Patent number: 8695007
    Abstract: A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Wada, Shuhei Matsumoto, Hironori Inoue, Kenichiro Yamato
  • Publication number: 20130347000
    Abstract: Computer including a plurality of physical CPUs, a plurality of virtual computers which execute predetermined processing and to which one of the plurality of physical CPUs is assigned, and a virtual computer control component able to cause the plurality of physical CPUs to execute overhead processing required by plurality of virtual computers. Virtual computer control component configured to: (A) upon causing the physical CPU, in which processing of the virtual computer is in a running state, to execute overhead processing, measure a run time used by the physical CPU to manage a cumulative run time, for each of the physical CPUs; and (B) upon causing the overhead processing to be executed subsequent to the (A), select a physical CPU in which the cumulative run time is smallest as the physical CPU to execute the overhead processing.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 26, 2013
    Inventors: Hironori INOUE, Shuhei MATSUMOTO
  • Publication number: 20130159936
    Abstract: In a content display device (1) of the present invention, a scrolling processing section (107) causes a scrolling movement of a currently-displayed shelf face (11) in a lengthwise direction to be displayed in a case where a second input operation instructing display of the currently-displayed shelf face (11) in a different position in the lengthwise direction is carried out via an input operation section (111). A rotation processing section (106) causes rotation of a bookshelf object (10) on a central axis of the bookshelf object (10) to be displayed in a case where a first input operation instructing display of a shelf face (11) different from the currently-displayed shelf face (11) is carried out via the input operation section (111).
    Type: Application
    Filed: September 21, 2011
    Publication date: June 20, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Sunao Yamaguchi, Shinichiro Ota, Yu Matsumoto, Hironori Inoue, Masayuki Nakazawa, Toshiroh Mukai
  • Patent number: 8464258
    Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: June 11, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue
  • Patent number: 8423999
    Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: April 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
  • Patent number: 8266629
    Abstract: Attempts are made to reduce the system overhead generated at the time of context save/restore processing to perform process switching in a virtual machine system. In a CPU occupancy mode that a physical CPU is exclusively allocated to virtual machines, a logical CPU process running on the physical CPU is static, so that it is not necessary to save/restore the context every time the processes are switched. When a switching source process is a logical CPU process in a CPU occupancy mode, a context save is temporarily suspended. When switching to the same logical CPU process is made again continuously, save/restore is skipped. When the logical CPU process of a VMM control VM runs in that period, the logical CPU process whose save is delayed is recorded and saved late.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: September 11, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Inoue, Shuhei Matsumoto
  • Publication number: 20120174114
    Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.
    Type: Application
    Filed: December 6, 2011
    Publication date: July 5, 2012
    Inventors: SHUHEI MATSUMOTO, Hironori Inoue, Shintaro Wada
  • Publication number: 20110302579
    Abstract: When the number of logical CPUs increases as the number of LPARs increases, a physical CPU amount which a hypervisor uses will increase and thus the physical CPU resource cannot be effectively utilized. Grouping of LPARs and physical CPUs is performed and a logical CPU to which a physical CPU is allocated is selected from logical CPUs of an LPAR within a group.
    Type: Application
    Filed: April 26, 2011
    Publication date: December 8, 2011
    Inventors: Makiko Shinohara, Shuhei Matsumoto, Hironori Inoue