Abstract: There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of the corresponding output pin and a slave channel provided in correspondence to a different output pin from that of the master channel to sample an output signal of the corresponding output pin, wherein the master channel has a frequency divider for generating a frequency-divided clock by dividing a source synchronous clock outputted from the device-under-test, a sampling section for sampling the corresponding output signal based on the frequency-divided clock and a distributing section for distributing the frequency-divided clock to the slave channel, and the slave channel has a sampling section for sampling the corresponding output signal based on the frequency-divided clock received from the master channel.

Abstract: A test apparatus for testing electronic devices is provided which includes a plurality of signal sources to supply an output signal to test electronic devices according to an input signal, a loop circuit to make the output signal loop and to input the looped signal to each of the signal sources having output the output signal as an input signal, a counter section to measure a period between inputting of the input signal and inputting the looped signal in each of the signal sources, and a controlling section to control timing at which each of the signal sources supplies the output signal so that a period measured by the counter section in each of the signal sources be substantially same.

Abstract: There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of the corresponding output pin and a slave channel provided in correspondence to a different output pin from that of the master channel to sample an output signal of the corresponding output pin, wherein the master channel has a frequency divider for generating a frequency-divided clock by dividing a source synchronous clock outputted from the device-under-test, a sampling section for sampling the corresponding output signal based on the frequency-divided clock and a distributing section for distributing the frequency-divided clock to the slave channel, and the slave channel has a sampling section for sampling the corresponding output signal based on the frequency-divided clock received from the master channel.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation circuit operable to generate timing signals that cause the plurality of test modules to operate based on the reference clock; a plurality of timing sources being provided in response to the plurality of test modules and operable to supply the timing signals to the corresponding test modules; and a control unit operable to control phases of the timing signals supplied to each of the test modules by the plurality of timing sources so that timings at which each of the test modules outputs the test patterns according to the timing signals are made to be equal.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation circuit operable to generate timing signals that cause the plurality of test modules to operate based on the reference clock; a plurality of timing sources being provided in response to the plurality of test modules and operable to supply the timing signals to the corresponding test modules; and a control unit operable to control phases of the timing signals supplied to each of the test modules by the plurality of timing sources so that timings at which each of the test modules outputs the test patterns according to the timing signals are made to be equal.

Abstract: A test apparatus for testing electronic devices is provided which includes a plurality of signal sources to supply an output signal to test electronic devices according to an input signal, a loop circuit to make the output signal loop and to input the looped signal to each of the signal sources having output the output signal as an input signal, a counter section to measure a period between inputting of the input signal and inputting the looped signal in each of the signal sources, and a controlling section to control timing at which each of the signal sources supplies the output signal so that a period measured by the counter section in each of the signal sources be substantially same.