Abstract: A measurement system includes a first feature point data generator, a second feature point data generator, and a calculator. The first feature point data generator generates first feature point data from first image data or from first shape data. The first image data is obtained from imaging of a measurement target and includes a predetermined portion of the measurement target. The first shape data is generated based on the first image data. The second feature point data generator generates second feature point data from second image data different from the first image data or from second shape data. The calculator calculates a positional correspondence of the predetermined portion of the measurement target between the first image data and the second image data or between the first shape data and the second shape data based on the first feature point data and the second feature point data.

Abstract: An X-ray inspection apparatus is used for an inspection of a substrate, and the X-ray inspection apparatus includes an image acquisition unit that acquires a plurality of tomographic images for the substrate, an image extraction unit that extracts, from a data set obtained based on the plurality of tomographic images, an inspection tomographic image that is a target for determining whether the substrate is acceptable or not, a saved data generation unit that generates predetermined saved data including at least the inspection tomographic image, and a saved data storage unit that stores the saved data.

Abstract: There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatus 100 includes a fusion step (FIG. 2/STEP026) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.

Abstract: A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.

Abstract: It is provided a processor system comprising at least one processor core provided on a semiconductor chip and including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes the task in a case of confirming that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and stores the data subjected to the acceleration processing into the data area, and further writes a flag indicating that the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, the task corresponding to a flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

Abstract: An X-ray inspection apparatus includes a 3D processing unit that performs 3D imaging of a first area in an inspection area, a 2D processing unit that performs 2D imaging of a second area in the inspection area, an extraction unit that extracts 3D information for a first inspection target from a 3D image of the first area, and 2D information for a second inspection target from a 2D image of the second area, a 3D information estimation unit that estimates 3D information for the second inspection target using the extracted 3D information for the first inspection target, and an inspection unit that inspects the second inspection target using the 2D information for the second inspection target and the estimated 3D information for the second inspection target.

Abstract: There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatus 100 includes a fusion step (FIG. 2/STEP026) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.

Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.

Abstract: In one or more embodiments, a method of generating a code by a compiler includes: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in the program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating the code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and the code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory.

Abstract: An X-ray inspection apparatus includes a 3D processing unit that performs 3D imaging of a first area in an inspection area, a 2D processing unit that performs 2D imaging of a second area in the inspection area, an extraction unit that extracts 3D information for a first inspection target from a 3D image of the first area, and 2D information for a second inspection target from a 2D image of the second area, a 3D information estimation unit that estimates 3D information for the second inspection target using the extracted 3D information for the first inspection target, and an inspection unit that inspects the second inspection target using the 2D information for the second inspection target and the estimated 3D information for the second inspection target.

Abstract: It is provided a processor system comprising at least one processor core provided on a semiconductor chip and including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes the task in a case of confirming that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and stores the data subjected to the acceleration processing into the data area, and further writes a flag indicating that the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, the task corresponding to a flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

Abstract: It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.

Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.

Abstract: A parallelization compiling method includes analyzing a sequential program prepared for a single-core processor; dividing the sequential program into a plurality of processes based on an analysis result; and generating a parallelized program, which is subjected to a parallelized execution by a multi-core processor, from the plurality of processes. The generating of the parallelized program includes compiling the plurality of processes under an execution order restriction defined based on a predetermined parameter.

Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.

Abstract: A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.

Abstract: A method of extracting parallelism of an original program by a computer includes: a process of determining whether or not a plurality of macro tasks to be executed after a condition of one conditional branch included in the original program is satisfied are executable in parallel; and a process of copying the conditional branch regarding which the macro tasks are determined to be executable in parallel, to generate a plurality of conditional branches.

Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.

Abstract: It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.

Abstract: Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.