Patents by Inventor Hironori Kashimoto

Hironori Kashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7671382
    Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: March 2, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shingo Sudo, Tatsuo Ota, Nobutake Taniguchi, Hiroshi Yoshida, Hironori Kashimoto
  • Patent number: 7589412
    Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: September 15, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hironori Kashimoto, Tatsuo Ota, Shingo Sudo
  • Publication number: 20070215999
    Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.
    Type: Application
    Filed: September 27, 2006
    Publication date: September 20, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hironori KASHIMOTO, Tatsuo Ota, Shingo Sudo
  • Publication number: 20070138624
    Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.
    Type: Application
    Filed: August 3, 2006
    Publication date: June 21, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shingo Sudo, Tatsuo Ota, Nobutake Taniguchi, Hiroshi Yoshida, Hironori Kashimoto