Abstract: A resin composition for an aqueous ink includes a base resin, an aqueous dispersion medium, and an emulsifier. The base resin includes a rosin-modified alkyd resin. The emulsifier includes an anionic emulsifier and a nonionic emulsifier. The anionic emulsifier includes an oxyalkylene-containing anionic emulsifier. An HLB value of the nonionic emulsifier is 16.0 or more and 20.0 or less.

Abstract: In a resin for an active-energy-ray-curable ink containing a rosin-modified polyester resin, the rosin-modified polyester resin includes a reaction product of a material component containing rosins, a dibasic acid, and a polyol. The rosin-modified polyester resin has an ester bond in an amount of 5.20 mol/kg or more and 7.20 mol/kg or less. The rosin-modified polyester resin has an acid value of 1 mgKOH/g or more and 30 mgKOH/g or less. The rosin-modified polyester resin has a hydroxyl value of 1 mgKOH/g or more and 40 mgKOH/g or less.

Abstract: In a resin for an active-energy-ray-curable ink containing a rosin-modified polyester resin, the rosin-modified polyester resin includes a reaction product of a material component containing rosins, a dibasic acid, and a polyol. The rosin-modified polyester resin has an ester bond in an amount of 5.20 mol/kg or more and 7.20 mol/kg or less. The rosin-modified polyester resin has an acid value of 1 mgKOH/g or more and 30 mgKOH/g or less. The rosin-modified polyester resin has a hydroxyl value of 1 mgKOH/g or more and 40 mgKOH/g or less.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: Dendritic cell precursor populations, dendritic cell populations derived therefrom, methods for isolating, expanding and using are disclosed.

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: Dendritic cell precursor populations, dendritic cell populations derived therefrom, methods for isolating, expanding and using are disclosed.

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract: A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved.

Abstract: A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.

Abstract: A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.

Abstract: There is provided a semiconductor device comprising a semiconductor chip and an electronic part disposed adjacent to each other, wherein a terminal is provided on the side of each of the semiconductor chip and the electronic part, and the terminal is electrically connected to the other terminal in the state where the sides of the semiconductor chip and the electronic part approach to each other. Thereby, the size of the entire semiconductor device can be reduced, and the wiring path can be shortened significantly to improve electrical properties.