Abstract: A liquid crystal drive device includes: a frame memory retaining image information of a second frame immediately preceding a first frame; a first calculator calculating a first difference between image information of the first frame and the image information of the second frame; an edge enhancement processor performing edge enhancement processing of the first frame for each of pixels of the first frame and outputting edge enhancement image information; a selector selecting and outputting the edge enhancement image information or image information of the first frame; a second calculator calculating a second difference between an output of the selector and the image information of the second frame; an enhancement coefficient calculator multiplying an output of the second calculator by an enhancement correction coefficient; and a third calculator calculating sum information by adding together an output of the enhancement coefficient calculator and the image information of the second frame.

Abstract: A liquid crystal drive apparatus includes: a storage unit storing an enhancement correction coefficient having (1/2n)×m below a decimal point where n is 3 or 4, and m is an integer which is at least 0 and less than 2n; a frame memory holding digital image information of a second frame located one frame before a first frame; a first computation unit computing a difference between digital image information of the first frame and digital image information of the second frame; a second computation unit computing enhancement image information for conducting enhancement display of an image on a liquid crystal panel on the basis of the difference and the enhancement correction coefficient; a third computation unit computing addition information by adding the digital image information of the second frame to the enhancement image information; and a drive signal generation unit generating a drive signal on the basis of the addition information to drive the liquid crystal panel.

Abstract: An image processing circuit has a color information converter configured to convert image data including a plurality of color information into luminance data and color difference data, an activity detector whether amount of activity predetermined according to differences between the luminance data in a plurality of pixels in each of pixel blocks and differences between the color difference data in the plurality of pixels exceeds a predetermined first threshold value for each pixel block including a plurality of pixels adjacent to each other, and a encoding unit configured to perform a first encoding process by generating m (m is an integer of three or larger) representative values corresponding to the luminance data and the color difference data in the plurality of pixels in the pixel block that the activity detector determines to exceed the first threshold value, and perform a second encoding process by generating n (n is an integer of two or more and the integer larger than m) representative values correspo

Abstract: An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.

Abstract: A liquid crystal drive device includes: a frame memory retaining image information of a second frame immediately preceding a first frame; a first calculator calculating a first difference between image information of the first frame and the image information of the second frame; an edge enhancement processor performing edge enhancement processing of the first frame for each of pixels of the first frame and outputting edge enhancement image information; a selector selecting and outputting the edge enhancement image information or image information of the first frame; a second calculator calculating a second difference between an output of the selector and the image information of the second frame; an enhancement coefficient calculator multiplying an output of the second calculator by an enhancement correction coefficient; and a third calculator calculating sum information by adding together an output of the enhancement coefficient calculator and the image information of the second frame.

Abstract: A display driver for sending display data to a display panel includes a sampling circuit and a selector. The sampling circuit receives moving image data and a sampling signal generated by a write signal and an address designated with an address decoder and captures the moving image data on the basis of the sampling signal. The selector receives still image data, a selecting signal and the moving image data captured by the sampling circuit and selects one of the still image data and the moving image data on the basis of the selecting signal.

Abstract: A liquid crystal drive apparatus includes: a storage unit storing an enhancement correction coefficient having (1/2n)×m below a decimal point where n is 3 or 4, and m is an integer which is at least 0 and less than 2n; a frame memory holding digital image information of a second frame located one frame before a first frame; a first computation unit computing a difference between digital image information of the first frame and digital image information of the second frame; a second computation unit computing enhancement image information for conducting enhancement display of an image on a liquid crystal panel on the basis of the difference and the enhancement correction coefficient; a third computation unit computing addition information by adding the digital image information of the second frame to the enhancement image information; and a drive signal generation unit generating a drive signal on the basis of the addition information to drive the liquid crystal panel.

Abstract: There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.

Abstract: There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.

Abstract: A liquid crystal display device comprising: a memory which receives an image signal, and which stores image data; and a correction data generation circuit that performs overdrive processing when the image data is a moving image, the correction data generation circuit having: a subtracter which performs subtraction processing after receiving previous frame image data outputted from the memory and current frame image data; a multiplier which performs multiplication processing by a predetermined multiplication factor after receiving a result of subtraction by the subtracter; and an adder which performs addition processing after receiving a result of multiplication by the multiplier and the current frame image data or the previous frame image data outputted from the memory.

Abstract: An image processing circuit has a color information converter configured to convert image data including a plurality of color information into luminance data and color difference data, an activity detector whether amount of activity predetermined according to differences between the luminance data in a plurality of pixels in each of pixel blocks and differences between the color difference data in the plurality of pixels exceeds a predetermined first threshold value for each pixel block including a plurality of pixels adjacent to each other, and a encoding unit configured to perform a first encoding process by generating m (m is an integer of three or larger) representative values corresponding to the luminance data and the color difference data in the plurality of pixels in the pixel block that the activity detector determines to exceed the first threshold value, and perform a second encoding process by generating n (n is an integer of two or more and the integer larger than m) representative values correspo

Abstract: An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.

Abstract: A differential amplifying circuit according to the present invention, comprising: a first differential pair having first and second transistors of the same conduction type, which outputs differential output signals in accordance with differential input signals supplied to gate terminals of said first and second transistors from differential output terminals; a second differential pair having third and fourth transistors having the same conduction type as that of said first and second transistors with threshold voltages different from each other, which outputs differential output signals in accordance with said differential input signals supplied to gate terminals of said third and fourth transistors from said differential output terminals; a bias supply part which supplies bias current to said first and second differential parts; and a differential pair control part which controls whether or not to operate said second differential pair.

Abstract: There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.

Abstract: There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.

Abstract: A differential amplifying circuit according to the present invention, comprising: a first differential pair having first and second transistors of the same conduction type, which outputs differential output signals in accordance with differential input signals supplied to gate terminals of said first and second transistors from differential output terminals; a second differential pair having third and fourth transistors having the same conduction type as that of said first and second transistors with threshold voltages different from each other, which outputs differential output signals in accordance with said differential input signals supplied to gate terminals of said third and fourth transistors from said differential output terminals; a bias supply part which supplies bias current to said first and second differential parts; and a differential pair control part which controls whether or not to operate said second differential pair.

Abstract: In an amplifier device, a negative output voltage (−) of a differential amplifier stage corresponding to an input signal voltage (Vin) is supplied to the gate of Output transistor M25 for charging electrical charges to Capacitive load (80). A current corresponding to a positive output voltage (+) of the differential amplifier stage is supplied to Node (A) through which the gate of Output transistor M26 for discharging electrical charges from Capacitive load (80) is connected to Constant current source (4). This current becomes a value (Iy+&Dgr;I) according to the voltage (Vin). By changing the gate voltage of Output transistor M26, it enters ON, and the electrical charges are discharged as a current I3 from Capacitive load (80). The voltage (Vin) is converted to a current by Voltage-current converter (1), and Current-voltage converter (2) then converts this current to a voltage.

Abstract: There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.

Abstract: In an amplifier device, a negative output voltage (−) of a differential amplifier stage corresponding to an input signal voltage (Vin) is supplied to the gate of Output transistor M25 for charging electrical charges to Capacitive load (80). A current corresponding to a positive output voltage (+) of the differential amplifier stage is supplied to Node (A) through which the gate of Output transistor M26 for discharging electrical charges from Capacitive load (80) is connected to Constant current source (4). This current becomes a value (Iy+&Dgr;I) according to the voltage (Vin). By changing the gate voltage of Output transistor M26, it enters ON, and the electrical charges are discharged as a current I3 from Capacitive load (80). The voltage (Vin) is converted to a current by Voltage-current converter (1), and Current-voltage converter (2) then converts this current to a voltage.

Abstract: An offset detecting circuit 10 includes: a sample hold circuit 12 for holding a reference voltage Vref; and a buffer amplifier 13 having two pairs of input terminals. The reference voltage Vref is applied to at least one input terminal of one pair of the two input terminal pairs, and an output signal of the sample hold circuit 12 and an output signal VDout of the buffer amplifier 13 are applied to the other pair of the two input terminal pairs of the buffer amplifier 13, respectively. Further, an output circuit is composed of this offset detecting circuit 10 and a signal voltage outputting circuit 20 configured in the same way as the offset detecting circuit 10. The signal voltage outputting circuit 20 corrects the offset of a signal Vin inputted thereto on the basis of an offset voltage V between the reference voltage Vref and the output voltage VDout supplied from the offset voltage detecting circuit 10.