Patents by Inventor Hironori TERAZAWA

Hironori TERAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device used for adjustment of output of a hall element
    Patent number: 8629521
    Abstract: A semiconductor device includes a Hall element, which is switched between a first and second mode. In the first mode, connection A between a first and second resistor and connection C between a third and fourth resistor are set to Vcc or GND. Connection D between the first and fourth resistor and connection B between the second and third resistor are set as output terminals. In the second mode, D and B are set to Vcc or GND and A and C are set as output terminals. When a first line placed along the second resistor and connected to A is set at Vcc in the first mode, a second line placed along the fourth resistor and connected to D is set at Vcc in the second mode. When the first line is set at GND in first mode, the second line is set at GND in the second mode.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 14, 2014
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Takashi Ogawa, Hironori Terazawa, Akihiro Hasegawa, Takashi Naruse, Yuuhei Mouri
  • Offset cancelling circuit
    Patent number: 8502530
    Abstract: In an offset cancelling circuit of a Hall element, a voltage is applied from four directions and from outside such that a current flowing in the Hall element is switched by 90°, to set a first state through a fourth state, and output voltages of the Hall element in the first state through the fourth state are averaged.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 6, 2013
    Assignees: Sanyo Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Takashi Ogawa, Hironori Terazawa, Takahisa Nakai
  • SEMICONDUCTOR DEVICE
    Publication number: 20120049303
    Abstract: A semiconductor device includes a Hall element, which is switched between a first and second mode. In the first mode, connection A between a first and second resistor and connection C between a third and fourth resistor are set to Vcc or GND. Connection D between the first and fourth resistor and connection B between the second and third resistor are set as output terminals. In the second mode, D and B are set to Vcc or GND and A and C are set as output terminals. When a first line placed along the second resistor and connected to A is set at Vcc in the first mode, a second line placed along the fourth resistor and connected to D is set at Vcc in the second mode. When the first line is set at GND in first mode, the second line is set at GND in the second mode.
    Type: Application
    Filed: August 23, 2011
    Publication date: March 1, 2012
    Applicant: ON SEMICONDUCTOR TRADING, LTD.
    Inventors: Takashi Ogawa, Hironori Terazawa, Akihiro Hasegawa, Takashi Naruse, Yuuhei Mouri
  • OFFSET CANCELLING CIRCUIT
    Publication number: 20100308801
    Abstract: In an offset cancelling circuit of a Hall element, a voltage is applied from four directions and from outside such that a current flowing in the Hall element is switched by 90°, to set a first state through a fourth state, and output voltages of the Hall element in the first state through the fourth state are averaged.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Takashi OGAWA, Hironori TERAZAWA, Takahisa NAKAI