Patents by Inventor HIRONORI TSUBOTA

HIRONORI TSUBOTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip resistor and method for manufacturing the same
    Patent number: 10340063
    Abstract: A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 2, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuharu Kinoshita, Shoji Hoshitoku, Hironori Tsubota, Yasuhiro Kashima
  • CHIP RESISTOR AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20180096759
    Abstract: A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.
    Type: Application
    Filed: April 26, 2017
    Publication date: April 5, 2018
    Inventors: YASUHARU KINOSHITA, SHOJI HOSHITOKU, HIRONORI TSUBOTA, YASUHIRO KASHIMA