Abstract: A system according to embodiments comprises first to third acquisition units and first and second creation units. The first acquisition unit may acquire event information including timeline information about an execution time or an execution order of at least one event. The second acquisition unit may acquire axis information including first axis information for deciding an first coordinate axis of a timeline about the execution time or the execution order of the event. The third acquisition unit may acquire event specific information for specifying the event information. The first creation unit may create a first axis object representing the first coordinate axis based on the axis information.

Abstract: A system according to embodiments comprises first to third acquisition units and first and second creation units. The first acquisition unit may acquire event information including timeline information about an execution time or an execution order of at least one event. The second acquisition unit may acquire axis information including first axis information for deciding an first coordinate axis of a timeline about the execution time or the execution order of the event. The third acquisition unit may acquire event specific information for specifying the event information. The first creation unit may create a first axis object representing the first coordinate axis based on the axis information.

Abstract: An apparatus for designing a system LSI including a configurable processor includes a series of processing programs used for the design of the system LSI, each of the processing programs configured to input a file outputted from a previous processing program and to output a file to be inputted to the following processing program. Each of the processing programs includes: an integrity information storage section configured to store integrity information between the processing programs; an integrity information identification section configured to identify integrity information included in the inputted file; an integrity verification section configured to verify whether or not integrity is maintained between the processing programs by comparing the identified integrity information and the integrity information stored in the integrity information storage section; and an integrity information addition section configured to add integrity information into the output file and then output the output file.

Abstract: An apparatus for designing a system LSI including a configurable processor includes a series of processing programs used for the design of the system LSI, each of the processing programs configured to input a file outputted from a previous processing program and to output a file to be inputted to the following processing program. Each of the processing programs includes: an integrity information storage section configured to store integrity information between the processing programs; an integrity information identification section configured to identify integrity information included in the inputted file; an integrity verification section configured to verify whether or not integrity is maintained between the processing programs by comparing the identified integrity information and the integrity information stored in the integrity information storage section; and an integrity information addition section configured to add integrity information into the output file and then output the output file.

Abstract: A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S101); a test vector generation data preparation step of preparing data required for generating test vectors (S103); and a test vector generation step of generating test vectors by the use of said data (S105).

Abstract: A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S101); a test vector generation data preparation step of preparing data required for generating test vectors (S103); and a test vector generation step of generating test vectors by the use of said data (S105).

Abstract: A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S101); a test vector generation data preparation step of preparing data required for generating test vectors (S103); and a test vector generation step of generating test vectors by the use of said data (S105).

Abstract: A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S101); a test vector generation data preparation step of preparing data required for generating test vectors (S103); and a test vector generation step of generating test vectors by the use of said data (S105).