Patents by Inventor Hironori Yoshioka
Hironori Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11926927Abstract: Developed and provided is a method of collecting a large amount of high-quality bagworm silk threads having no contaminant from bagworm nests in a convenient manner and at low cost. The habit of bagworms is utilized to allow a bagworm to build a nest using solvent-soluble substances or thermally meltable substances as nest materials, followed by dissolving or melting the nest materials to separate the nest material from the bagworm silk threads, whereby only pure bagworm silk threads constituting the bagworm nest can be obtained.Type: GrantFiled: December 18, 2018Date of Patent: March 12, 2024Assignees: NATIONAL AGRICULTURE AND FOOD RESEARCH ORGANIZATION, KOWA COMPANY, LTD.Inventors: Taiyo Yoshioka, Tsunenori Kameda, Akimune Asanuma, Hironori Sassa
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Publication number: 20240039688Abstract: A signal generation device includes m transceivers, a usage amount determination unit that executes a usage amount determination process that determines the usage amount of the FIFO of each transceiver, and a phase adjustment unit that adjusts the phase of the read clock signal for the FIFO. The signal generation device performs the second usage amount determination process on the condition that the count that the usage amount of the FIFO of each transceiver is determined to be less than the usage amount threshold by the first usage amount determination process consecutively reaches the first determination count, and terminates the adjustment of the phase of the read clock signal on the condition that the count that the usage amount of the FIFO of each transceiver is determined by the second usage amount determination process to be greater than the usage amount threshold consecutively reaches the second determination count.Type: ApplicationFiled: June 13, 2023Publication date: February 1, 2024Inventors: Hironori YOSHIOKA, Tatsuya IWAI
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Patent number: 7994006Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: GrantFiled: November 14, 2008Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7564107Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.Type: GrantFiled: September 9, 2004Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
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Publication number: 20090075433Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: ApplicationFiled: November 14, 2008Publication date: March 19, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7462541Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminating portion side.Type: GrantFiled: October 17, 2005Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7301202Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: GrantFiled: June 14, 2005Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Patent number: 7259426Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.Type: GrantFiled: March 31, 2005Date of Patent: August 21, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 7253507Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.Type: GrantFiled: October 29, 2004Date of Patent: August 7, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Kouzuki, Satoshi Aida, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20060138536Abstract: A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.Type: ApplicationFiled: June 14, 2005Publication date: June 29, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kouzuki, Hideki Okumura, Wataru Saito, Masaru Izumisawa, Masahiko Shiomi, Hitoshi Kobayashi, Kenichi Tokano, Satoshi Yanagisawa, Hironori Yoshioka, Manabu Kimura
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Publication number: 20060097313Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar layer of a second conductivity type provided adjacent to the first semiconductor pillar layer; a semiconductor region of the first conductivity type provided between the semiconductor layer and the second semiconductor pillar layer, the semiconductor region having a lower impurity concentration than the semiconductor layer; a semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a semiconductor source region of the first conductivity type selectively provided in the surface of the semiconductor base layer; a gate insulating film provided on the semiconductor base layer between the semiconductor source region and the first semiconductor pillar layer; and a gate electrode provided on the gate insulating film.Type: ApplicationFiled: February 22, 2005Publication date: May 11, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20060049459Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviatesType: ApplicationFiled: October 17, 2005Publication date: March 9, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20060017096Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.Type: ApplicationFiled: September 9, 2004Publication date: January 26, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Yanagisawa, Satoshi Aida, Shigeo Kouzuki, Hironori Yoshioka, Ichiro Omura, Wataru Saito
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Patent number: 6972460Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.Type: GrantFiled: October 8, 2003Date of Patent: December 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20050250322Abstract: There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.Type: ApplicationFiled: March 31, 2005Publication date: November 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20050194638Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.Type: ApplicationFiled: October 29, 2004Publication date: September 8, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Kouzuki, Satoshi Aida, Satoshi Yanagisawa, Masaru Izumisawa, Hironori Yoshioka
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Patent number: 6849900Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first coType: GrantFiled: June 27, 2003Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka, Wataru Saito
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Publication number: 20040251516Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviatesType: ApplicationFiled: October 8, 2003Publication date: December 16, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka
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Publication number: 20040206989Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first coType: ApplicationFiled: June 27, 2003Publication date: October 21, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa, Hironori Yoshioka, Wataru Saito