Patents by Inventor Hiroo ANAN

Hiroo ANAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083183
    Abstract: An electronic component includes: a variable capacitance element; a substrate that has the variable capacitance element; a connection pattern that is electrically connected to the variable capacitance element; and a sealing member that has permittivity lower than that of the substrate and has insulation resistance higher than that of the substrate. At least a part of the connection pattern is disposed on an outer surface of the sealing member.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 12, 2020
    Inventors: Toshihiko TAKAHATA, Hiroo ANAN
  • Patent number: 10180364
    Abstract: A load sensor includes: a substrate; a rib on the substrate; and two vertical transistors. Each vertical transistor includes: a gate electrode, a gate insulation film, and a semiconductor thin film on the side surface of the rib; a bottom electrode layer on a bottom of the substrate, on which the rib is not arranged, with contacting the semiconductor thin film; and a top electrode layer on a top of the rib with contacting the semiconductor thin film. Each vertical transistor flows current between the bottom electrode layer and the top electrode layer when a channel region is provided in the semiconductor thin film. Each straight line along normal line directions of the channel regions in the vertical transistors is arranged on a different side surface of the rib from each other, and has a predetermined angle between the straight lines.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 15, 2019
    Assignee: DENSO CORPORATION
    Inventors: Hiroo Anan, Takashi Inoue
  • Publication number: 20170199090
    Abstract: A load sensor includes: a substrate; a rib on the substrate; and two vertical transistors. Each vertical transistor includes: a gate electrode, a gate insulation film, and a semiconductor thin film on the side surface of the rib; a bottom electrode layer on a bottom of the substrate, on which the rib is not arranged, with contacting the semiconductor thin film; and a top electrode layer on a top of the rib with contacting the semiconductor thin film. Each vertical transistor flows current between the bottom electrode layer and the top electrode layer when a channel region is provided in the semiconductor thin film. Each straight line along normal line directions of the channel regions in the vertical transistors is arranged on a different side surface of the rib from each other, and has a predetermined angle between the straight lines.
    Type: Application
    Filed: August 21, 2015
    Publication date: July 13, 2017
    Inventors: Hiroo ANAN, Takashi INOUE