Patents by Inventor Hiroo Hayashi

Hiroo Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362561
    Abstract: A stator wherein the lead wire portion includes a root portion connected to the slot housed portion, disposed in a same-phase region which overlaps the coil end portion of the coil of a same phase as seen in the center axis direction, and disposed on an axially inner side with respect to the coil end portion, and a draw-out portion that projects in the center axis direction from a power source portion-side end portion of the root portion toward an axially outer side with respect to the coil end portion in the same-phase region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 14, 2022
    Assignees: AISIN CORPORATION, HAYASHI KOGYOSYO CO., LTD.
    Inventors: Toru Kuroyanagi, Takahiko Hobo, Hiroo Hayashi, Ko Kajita
  • Publication number: 20200220417
    Abstract: A stator wherein the lead wire portion includes a root portion connected to the slot housed portion, disposed in a same-phase region which overlaps the coil end portion of the coil of a same phase as seen in the center axis direction, and disposed on an axially inner side with respect to the coil end portion, and a draw-out portion that projects in the center axis direction from a power source portion-side end portion of the root portion toward an axially outer side with respect to the coil end portion in the same-phase region.
    Type: Application
    Filed: September 19, 2018
    Publication date: July 9, 2020
    Applicants: AISIN AW CO., LTD., HAYASHIKOGYOSYO CO., LTD.
    Inventors: Toru KUROYANAGI, Takahiko HOBO, Hiroo HAYASHI, Ko KAJITA
  • Patent number: 9081711
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 14, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8949572
    Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
  • Publication number: 20140164702
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8607024
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8429380
    Abstract: A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroo Hayashi
  • Publication number: 20130068388
    Abstract: A method of manufacturing a roll of sheet includes forming a layered sheet by combining a plurality of overlapped fiber sheets which is moving in a continuation direction and winding the layered sheet. The forming of the layered sheet includes performing a first compression in which a plurality of first regions and a plurality of second regions are disposed in an alternating manner in the continuation direction, the second regions lying along an intersecting direction and performing second compression in which among the first regions and the second regions, at least the first regions are compressed. The accumulating of the layered sheet includes forming a loop of the layered sheet by disposing the layered sheet along the peripheral surface of a rotatable roller. The winding of the layered sheet includes winding the layered sheet on a winding mandrel located downstream of the rotatable roller.
    Type: Application
    Filed: February 10, 2010
    Publication date: March 21, 2013
    Applicant: UNI-CHARM CORPORATION
    Inventor: Hiroo Hayashi
  • Patent number: 8145804
    Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 27, 2012
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
  • Publication number: 20110309098
    Abstract: An openable and closeable container that includes a container body having a take-out opening; an opening-closing lid provided on the container body swingably about a swing axis X-X on a base end side, the opening-closing lid opening/closing the take-out opening; and plate rubber (an elastic member) provided between the container body and the opening-closing lid. A spring body is provided on the base end side of the opening-closing lid and a sloping portion (a braking portion) with which the spring body comes into contact is provided on the container body side. The spring body is gradually compressed from the state where the opening-closing lid is closed toward the state where the opening-closing lid is opened.
    Type: Application
    Filed: October 29, 2009
    Publication date: December 22, 2011
    Inventors: Hiroo Hayashi, Takeshi Bandoh, Takahiro Ueda, Masaho Hayashi, Hiroshi Uematsu, Toshihiko Uenishi, Norio Ochi
  • Publication number: 20110231593
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Application
    Filed: December 1, 2010
    Publication date: September 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenta YASUFUKU, Shigeaki IWASA, Yasuhiko KUROSAWA, Hiroo HAYASHI, Seiji MAEDA, Mitsuo SAITO
  • Publication number: 20110072170
    Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
  • Patent number: 7913006
    Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
  • Publication number: 20110047349
    Abstract: A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled.
    Type: Application
    Filed: March 12, 2010
    Publication date: February 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroo HAYASHI
  • Publication number: 20100100684
    Abstract: A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.
    Type: Application
    Filed: October 16, 2009
    Publication date: April 22, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Atsushi Kameyama, Shigeaki Iwasa, Hiroo Hayashi, Mitsuo Saito
  • Publication number: 20100100685
    Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
    Type: Application
    Filed: October 16, 2009
    Publication date: April 22, 2010
    Applicant: Kabushihiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
  • Patent number: 7565512
    Abstract: Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set of multiplexers, each set corresponding to one of a set of instructions fetched in a cycle of a microprocessor, the number of multiplexers in each set equal to the number of bits of global history and each multiplexer within a set having a select signal corresponding to the same instruction to which that set of multiplexers corresponds.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: July 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroo Hayashi
  • Publication number: 20090172016
    Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.
    Type: Application
    Filed: March 6, 2009
    Publication date: July 2, 2009
    Inventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
  • Patent number: 7543091
    Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: June 2, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
  • Publication number: 20080189533
    Abstract: Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set of multiplexers, each set corresponding to one of a set of instructions fetched in a cycle of a microprocessor, the number of multiplexers in each set equal to the number of bits of global history and each multiplexer within a set having a select signal corresponding to the same instruction to which that set of multiplexers corresponds.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventor: Hiroo Hayashi