Patents by Inventor Hiroo Hayashi
Hiroo Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11362561Abstract: A stator wherein the lead wire portion includes a root portion connected to the slot housed portion, disposed in a same-phase region which overlaps the coil end portion of the coil of a same phase as seen in the center axis direction, and disposed on an axially inner side with respect to the coil end portion, and a draw-out portion that projects in the center axis direction from a power source portion-side end portion of the root portion toward an axially outer side with respect to the coil end portion in the same-phase region.Type: GrantFiled: September 19, 2018Date of Patent: June 14, 2022Assignees: AISIN CORPORATION, HAYASHI KOGYOSYO CO., LTD.Inventors: Toru Kuroyanagi, Takahiko Hobo, Hiroo Hayashi, Ko Kajita
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Publication number: 20200220417Abstract: A stator wherein the lead wire portion includes a root portion connected to the slot housed portion, disposed in a same-phase region which overlaps the coil end portion of the coil of a same phase as seen in the center axis direction, and disposed on an axially inner side with respect to the coil end portion, and a draw-out portion that projects in the center axis direction from a power source portion-side end portion of the root portion toward an axially outer side with respect to the coil end portion in the same-phase region.Type: ApplicationFiled: September 19, 2018Publication date: July 9, 2020Applicants: AISIN AW CO., LTD., HAYASHIKOGYOSYO CO., LTD.Inventors: Toru KUROYANAGI, Takahiko HOBO, Hiroo HAYASHI, Ko KAJITA
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Patent number: 9081711Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: GrantFiled: November 26, 2013Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Patent number: 8949572Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.Type: GrantFiled: October 16, 2009Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Publication number: 20140164702Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: ApplicationFiled: November 26, 2013Publication date: June 12, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Patent number: 8607024Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: GrantFiled: December 1, 2010Date of Patent: December 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
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Patent number: 8429380Abstract: A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled.Type: GrantFiled: March 12, 2010Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Hiroo Hayashi
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Publication number: 20130068388Abstract: A method of manufacturing a roll of sheet includes forming a layered sheet by combining a plurality of overlapped fiber sheets which is moving in a continuation direction and winding the layered sheet. The forming of the layered sheet includes performing a first compression in which a plurality of first regions and a plurality of second regions are disposed in an alternating manner in the continuation direction, the second regions lying along an intersecting direction and performing second compression in which among the first regions and the second regions, at least the first regions are compressed. The accumulating of the layered sheet includes forming a loop of the layered sheet by disposing the layered sheet along the peripheral surface of a rotatable roller. The winding of the layered sheet includes winding the layered sheet on a winding mandrel located downstream of the rotatable roller.Type: ApplicationFiled: February 10, 2010Publication date: March 21, 2013Applicant: UNI-CHARM CORPORATIONInventor: Hiroo Hayashi
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Patent number: 8145804Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: GrantFiled: September 21, 2009Date of Patent: March 27, 2012Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Publication number: 20110309098Abstract: An openable and closeable container that includes a container body having a take-out opening; an opening-closing lid provided on the container body swingably about a swing axis X-X on a base end side, the opening-closing lid opening/closing the take-out opening; and plate rubber (an elastic member) provided between the container body and the opening-closing lid. A spring body is provided on the base end side of the opening-closing lid and a sloping portion (a braking portion) with which the spring body comes into contact is provided on the container body side. The spring body is gradually compressed from the state where the opening-closing lid is closed toward the state where the opening-closing lid is opened.Type: ApplicationFiled: October 29, 2009Publication date: December 22, 2011Inventors: Hiroo Hayashi, Takeshi Bandoh, Takahiro Ueda, Masaho Hayashi, Hiroshi Uematsu, Toshihiko Uenishi, Norio Ochi
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Publication number: 20110231593Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: ApplicationFiled: December 1, 2010Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenta YASUFUKU, Shigeaki IWASA, Yasuhiko KUROSAWA, Hiroo HAYASHI, Seiji MAEDA, Mitsuo SAITO
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Publication number: 20110072170Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Patent number: 7913006Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.Type: GrantFiled: March 6, 2009Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
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Publication number: 20110047349Abstract: A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled.Type: ApplicationFiled: March 12, 2010Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroo HAYASHI
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Publication number: 20100100684Abstract: A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.Type: ApplicationFiled: October 16, 2009Publication date: April 22, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Atsushi Kameyama, Shigeaki Iwasa, Hiroo Hayashi, Mitsuo Saito
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Publication number: 20100100685Abstract: An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.Type: ApplicationFiled: October 16, 2009Publication date: April 22, 2010Applicant: Kabushihiki Kaisha ToshibaInventors: Yasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Patent number: 7565512Abstract: Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set of multiplexers, each set corresponding to one of a set of instructions fetched in a cycle of a microprocessor, the number of multiplexers in each set equal to the number of bits of global history and each multiplexer within a set having a select signal corresponding to the same instruction to which that set of multiplexers corresponds.Type: GrantFiled: February 2, 2007Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hiroo Hayashi
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Publication number: 20090172016Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.Type: ApplicationFiled: March 6, 2009Publication date: July 2, 2009Inventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
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Patent number: 7543091Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of each of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of each configuration object according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.Type: GrantFiled: September 22, 2004Date of Patent: June 2, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Hamaoka, Kazuko Ishibashi, Hiroo Hayashi
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Publication number: 20080189533Abstract: Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global history register operable to store a global history. More specifically, in one embodiment the global history logic comprises a set of multiplexers, each set corresponding to one of a set of instructions fetched in a cycle of a microprocessor, the number of multiplexers in each set equal to the number of bits of global history and each multiplexer within a set having a select signal corresponding to the same instruction to which that set of multiplexers corresponds.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Inventor: Hiroo Hayashi