Abstract: A metal fine particle is adhere to a predetermined location on a substrate. A resist film containing a metallic compound dispersed therein is formed on a substrate (101). A patterning of the resist film is conducted by a lithography. The substrate (101) having the patterned resist formed thereon is heated within an oxygen atmosphere to adhere a metal fine particle (106) to the surface of the substrate (101), while removing the resin in the patterned resist.

Abstract: When a predetermined voltage is applied between electrodes (302), metal ions deposit in a solid electrolyte (308), and thereby a conduction channel (310) is formed therein. The solid electrolyte switch (300) is thus turned on. Because this deposition mechanism is reversible, application of reverse voltage between the electrodes of the solid electrolyte switch (300) already turned on makes the deposited metal atoms to migrate in the solid electrolyte to thereby thin the conduction channel 300, thereby the channel finally disappears, and the solid electrolyte switch (300) is turned into a non-conductive state. Use of this switch successfully realizes an IC tag which can automatically be nullified without artificial nullification.

Abstract: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes a catalyst portion (55) containing a second material which is different from the first material. The first material includes a metal containing at least one of elements selected from the second group to the fourteenth group of the periodic table or a compound thereof. The second material is a catalyst which grows carbon nanotubes in a vapor phase.

Abstract: Scale down design has posed problems in an increase in the resistance value of an interconnection structure and a decrease in the resistance to electromigration and stress migration. The present invention provides an interconnection structure of a high-reliability semiconductor device which has a low resistance value even in the case of scale down design and does not produce electromigration or stress migration, and a method of manufacturing the interconnection structure. Provided are a semiconductor device which has an interconnection or a connection plug, both of which are fabricated from a mixture of a metal and carbon nanotubes, in an interconnection trench or a via hole, both of which are formed on an insulating film on a substrate on which a semiconductor device element is formed, and a method of manufacturing this semiconductor device.

Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

Abstract: When a predetermined voltage is applied between electrodes (302), metal ions deposit in a solid electrolyte (308), and thereby a conduction channel (310) is formed therein. The solid electrolyte switch (300) is thus turned on. Because this deposition mechanism is reversible, application of reverse voltage between the electrodes of the solid electrolyte switch (300) already turned on makes the deposited metal atoms to migrate in the solid electrolyte to thereby thin the conduction channel 300, thereby the channel finally disappears, and the solid electrolyte switch (300) is turned into a non-conductive state. Use of this switch successfully realizes an IC tag which can automatically be nullified without artificial nullification.

Abstract: A metal fine particle is adhere to a predetermined location on a substrate. A resist film containing a metallic compound dispersed therein is formed on a substrate (101). A patterning of the resist film is conducted by a lithography. The substrate (101) having the patterned resist formed thereon is heated within an oxygen atmosphere to adhere a metal fine particle (106) to the surface of the substrate (101), while removing the resin in the patterned resist.

Abstract: A catalyst supporting substrate includes a first region (54) which is formed on a substrate (50); and a second region (55) which is formed covering a part of the first region. The first region (54) includes a catalyst supporting portion (54a) containing a first material. The second region (55) includes a catalyst portion (55) containing a second material which is different from the first material. The first material includes a metal containing at least one of elements selected from the second group to the fourteenth group of the periodic table or a compound thereof. The second material is a catalyst which grows carbon nanotubes in a vapor phase.

Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

Abstract: A combination of a metal-based catalyst having a function as a catalyst for formation of graphite and a single-crystal substrate having a certain correspondence to the metal-based catalyst with respect to the crystal grain size and the crystal orientation thereof is used; the metal-based catalyst is dispersed on the single-crystal substrate; and a carbon material is fed to the substrate at any temperature not lower than 500° C. to thereby form single single-walled carbon nanotubes through vapor phase thermal decomposition growth on the substrate. More precisely, the invention of this application enables production of single-walled carbon nanotubes with controlled diameter, requiring neither a porous material nor catalyst particles for use as a catalyst carrier. One example of the combination of the metal-based catalyst and the single-crystal substrate is a combination of Fe and sapphire substrate.

Abstract: A cold cathode device is formed from a p-type semiconductor substrate 1. Two source/drain regions 2 are formed in the p-type semiconductor substrate 1, a silicon oxide film 3, which is an insulating film, is formed on the surface of the p-type semiconductor substrate 1 (the face where the source/drain regions 2 are formed), and a gate electrode 4 is formed on top of the silicon oxide film 3. Furthermore, a substrate electrode 5 is formed on the back surface of the p-type semiconductor substrate 1. The same voltages are applied to the source/drain regions 2 and the gate electrode 4, and a lower voltage is applied to the substrate electrode 5.

Abstract: An alignment mark for use in electron beam lithography for manufacturing a fine semiconductor structure by repeating a regrowth of a compound semiconductor layer and a fine process including electron beam exposure. The alignment mark includes a lower protection layer made of tungsten formed on a compound semiconductor substrate, a mark main body made of gold, chromium or platinum shaped into a desired pattern having a sharp edge profile which generates a detection signal of a mark position having a large gain, and an upper protection layer covering the mark main body and made of silicon oxide which does not react significantly with substances constituting a compound semiconductor layer. The mark main body has a thickness which is not less than 100 nm.