Patents by Inventor Hiroo Masuda
Hiroo Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5170374Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: April 7, 1992Date of Patent: December 8, 1992Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki
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Patent number: 5119332Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: April 30, 1990Date of Patent: June 2, 1992Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Hiroshi Kawamoto
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Patent number: 4860255Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: August 9, 1988Date of Patent: August 22, 1989Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4709353Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: December 15, 1986Date of Patent: November 24, 1987Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4656607Abstract: In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.Type: GrantFiled: July 19, 1984Date of Patent: April 7, 1987Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Toru Kaga, Hiroo Masuda
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Patent number: 4656492Abstract: An insulated gate field effect transistor is formed in one surface of a semiconductor substrate. The surface portion of a channel has an impurity distribution of the conduction type opposite to that of the substrate, which the deeper portion of the channel has an impurity distribution of the same conduction type as that of the substrate. Moreover, at least one of a source and a drain is formed of such an impurity layer of the conduction type opposite to that of the substrate as has its impurity distribution gently sloped by double diffusion processes.Type: GrantFiled: October 15, 1985Date of Patent: April 7, 1987Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Hiroo Masuda, Yoshiaki Kamigaki, Katsuhiro Shimohigashi, Eiji Takeda
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Patent number: 4646267Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETS formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: April 22, 1986Date of Patent: February 24, 1987Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4592022Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: July 19, 1985Date of Patent: May 27, 1986Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4539658Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: August 8, 1984Date of Patent: September 3, 1985Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4472792Abstract: A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.Type: GrantFiled: May 13, 1982Date of Patent: September 18, 1984Assignee: Hitachi, Ltd.Inventors: Katsuhiro Shimohigashi, Hiroo Masuda, Kunihiko Ikuzaki, Hiroshi Kawamoto
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Patent number: 4455495Abstract: A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.Type: GrantFiled: October 1, 1980Date of Patent: June 19, 1984Assignee: Hitachi, Ltd.Inventors: Toshiaki Masuhara, Osamu Minato, Katsuhiro Shimohigashi, Hiroo Masuda, Hideo Sunami, Yoshio Sakai, Yoshiaki Kamigaki, Eiji Takeda, Yoshimune Hagiwara
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Patent number: 4399519Abstract: In a dynamic monolithic memory including a plurality of memory cells each of which comprises a capacitance and a switching field-effect transistor, the source and drain electrodes of the transistor are connected to a data line and the capacitance, respectively. Upon reading a memory cell, the transistor is switched on when difference between the data line voltage and the word line voltage applied to a gate electrode of the transistor exceeds a threshold voltage of the transistor.Type: GrantFiled: September 17, 1980Date of Patent: August 16, 1983Assignee: Hitachi, Ltd.Inventors: Hiroo Masuda, Katsuhiro Shimohigashi
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Patent number: 4132997Abstract: A MOS type field effect transistor has an electrode, which is in the neighborhood of, but not in contact with, the drain diffusion region and is electrically connected with the surface portion of the semiconductor substrate in which the MOS type field effect transistor is formed, and whose potential is held at the rear surface potential of the semiconductor substrate, i. e., the substrate bias potential.Type: GrantFiled: January 31, 1977Date of Patent: January 2, 1979Assignee: Hitachi, Ltd.Inventors: Hiroo Masuda, Masaharu Kubo, Ryoichi Hori
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Patent number: 4086642Abstract: A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.Type: GrantFiled: January 13, 1976Date of Patent: April 25, 1978Assignee: Hitachi, Ltd.Inventors: Isao Yoshida, Ryoichi Hori, Hiroo Masuda, Osamu Minato, Jun Etoh, Masaaki Nakai