Patents by Inventor Hiroo Sakaba

Hiroo Sakaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ratioless type MIS logic circuit
    Patent number: 4107548
    Abstract: A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.
    Type: Grant
    Filed: March 4, 1977
    Date of Patent: August 15, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hiroo Sakaba, Kenzo Masuda