Patents by Inventor Hiroomi Eguchi
Hiroomi Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190109187Abstract: A switching element including: a bottom insulating layer disposed at a bottom of a trench; a side surface insulating film covering a side surface of the trench; and a gate electrode disposed inside the trench and insulated from a semiconductor substrate. The semiconductor substrate has a bottom region and a connection region. The bottom region is in contact with the bottom insulating layer. The connection region is in contact with the bottom insulating layer and the side surface insulating film, and connects a body region to the bottom region. An area of the connection region in which the bottom insulating layer contacts to the connection region includes an area with lower a second conductivity-type impurity concentration than a minimum value of the second conductivity-type impurity concentration in an area of the connection region in which the side surface insulating film contacts the connection region.Type: ApplicationFiled: April 18, 2017Publication date: April 11, 2019Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Tadashi MISUMI, Hiroomi EGUCHI, Yusuke YAMASHITA, Yasushi URAKAMI
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Patent number: 10002974Abstract: A Zener diode includes a semiconductor substrate, an anode electrode and a cathode electrode. The semiconductor substrate includes a p-type anode region, an n-type current path region and a drift region. The p-type anode region is connected to the anode electrode. The n-type current path region is in contact with the anode region. The drift region is in contact with the anode region and the current path region. The drift region is of an n type. The drift region has a lower n-type impurity concentration than the current path region. The drift region is connected to the cathode electrode directly or via another n-type region.Type: GrantFiled: October 30, 2014Date of Patent: June 19, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroomi Eguchi, Hiromichi Kinpara, Takashi Okawa, Satoshi Ikeda
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Patent number: 9985120Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.Type: GrantFiled: August 27, 2014Date of Patent: May 29, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Okawa, Hiroomi Eguchi, Hiromichi Kinpara, Satoshi Ikeda
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Patent number: 9978856Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.Type: GrantFiled: August 27, 2014Date of Patent: May 22, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Okawa, Hiroomi Eguchi, Hiromichi Kinpara, Satoshi Ikeda
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Publication number: 20160254390Abstract: A Zener diode includes a semiconductor substrate, an anode electrode and a cathode electrode. The semiconductor substrate includes a p-type anode region, an n-type current path region and a drift region. The p-type anode region is connected to the anode electrode. The n-type current path region is in contact with the anode region. The drift region is in contact with the anode region and the current path region. The drift region is of an n type. The drift region has a lower n-type impurity concentration than the current path region. The drift region is connected to the cathode electrode directly or via another n-type region.Type: ApplicationFiled: October 30, 2014Publication date: September 1, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroomi EGUCHI, Hiromichi KINPARA, Takashi OKAWA, Satoshi IKEDA
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Publication number: 20160240634Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.Type: ApplicationFiled: August 27, 2014Publication date: August 18, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi OKAWA, Hiroomi EGUCHI, Hiromichi KINPARA, Satoshi IKEDA
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Publication number: 20160233323Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.Type: ApplicationFiled: August 27, 2014Publication date: August 11, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi OKAWA, Hiroomi EGUCHI, Hiromichi KINPARA, Satoshi IKEDA
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Patent number: 9166040Abstract: A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.Type: GrantFiled: February 19, 2015Date of Patent: October 20, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Okawa, Hiroomi Eguchi, Hiromichi Kinpara, Satoshi Ikeda
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Publication number: 20150243778Abstract: A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.Type: ApplicationFiled: February 19, 2015Publication date: August 27, 2015Inventors: Takashi OKAWA, Hiroomi EGUCHI, Hiromichi KINPARA, Satoshi IKEDA
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Patent number: 9112024Abstract: A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view.Type: GrantFiled: May 17, 2011Date of Patent: August 18, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi Onogi, Hiroomi Eguchi, Takashi Okawa
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Patent number: 9048107Abstract: A semiconductor device includes a semiconductor layer; a first type of a first semiconductor element that is arranged in a first element region of the semiconductor layer, has first and second main electrodes, and switches current; and a second type of a second semiconductor element that is arranged in a second element region of the semiconductor layer, has third and fourth main electrodes, and freewheels the current. The first and second element regions are adjacent in a direction orthogonal to a direction in which current flows, and are formed in a loop shape over the entire element region when the semiconductor layer is viewed from above. The first main electrode is electrically connected to the third main electrode, and the second main electrode is electrically connected to the fourth main electrode.Type: GrantFiled: September 26, 2011Date of Patent: June 2, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hiroomi Eguchi, Atsushi Onogi, Takashi Okawa, Kiyoharu Hayakawa
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Patent number: 8871643Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.Type: GrantFiled: February 8, 2011Date of Patent: October 28, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hiroomi Eguchi, Takashi Okawa, Atsushi Onogi
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Publication number: 20140035036Abstract: A lateral semiconductor device including a semiconductor substrate; a buried oxide layer formed on the semiconductor substrate, and an active layer formed on the buried oxide layer. The active layer includes a first conductivity type well region, a second conductivity type well region, and a first conductivity type drift region interposed between the first conductivity type well region and the second conductivity type well region. A region where current flows because of carriers moving between the first conductivity type well region and the second conductivity type well region, and a region where no current flows are formed alternately between the first conductivity type well region and the second conductivity type well region, in a direction perpendicular to a carrier moving direction when viewed in a plan view.Type: ApplicationFiled: May 17, 2011Publication date: February 6, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi Onogi, Hiroomi Eguchi, Takashi Okawa
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Publication number: 20130309867Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.Type: ApplicationFiled: February 8, 2011Publication date: November 21, 2013Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroomi Eguchi, Takashi Okawa, Atsushi Onogi
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Publication number: 20130181252Abstract: A semiconductor device includes a semiconductor layer; a first type of a first semiconductor element that is arranged in a first element region of the semiconductor layer, has first and second main electrodes, and switches current; and a second type of a second semiconductor element that is arranged in a second element region of the semiconductor layer, has third and fourth main electrodes, and freewheels the current. The first and second element regions are adjacent in a direction orthogonal to a direction in which current flows, and are formed in a loop shape over the entire element region when the semiconductor layer is viewed from above. The first main electrode is electrically connected to the third main electrode, and the second main electrode is electrically connected to the fourth main electrode.Type: ApplicationFiled: September 26, 2011Publication date: July 18, 2013Inventors: Hiroomi Eguchi, Atsushi Onogi, Takashi Okawa, Kiyoharu Hayakawa