Abstract: A semiconductor device according to one aspect of the present invention includes a semiconductor substrate, an interlayer insulating film formed over the semiconductor substrate, a metal wiring formed over the interlayer insulating film, a protective insulating film formed on the metal wiring, and a resin film formed within a region having one side shorter than a predetermined length on the protective insulating film. The resin film covers all regions in which an interval of the metal wirings is equal to or less than a predetermined interval.

Abstract: A method of fabricating a semiconductor device is provided, which eliminates the possibility that the surface of a recess is contaminated before and after the process of forming a gate electrode, and which achieves sufficient controllability of the shape of a gate electrode. First and second dielectric layers, which have been formed successively to cover the recess of a semiconductor base material, are selectively removed by dry etching at approximately equal etch rates, thereby forming a gate opening that penetrates the second and first dielectric layers to reach the surface of the base material in the recess. A gate electrode with an approximately T-shaped cross section is formed to contact the surface of the base material in the recess by way of the gate opening. The second dielectric layer is selectively removed by wet etching at an etch rate sufficiently greater than an etch rate of the first dielectric layer, exposing the first dielectric layer.

Abstract: A semiconductor device has an interlayer insulation film formed on a first metal wiring and formed of an organic compound having a lower dielectric constant than that of SiO2, a second metal wiring formed on the interlayer insulation film, and an interlayer adhesion layer to improve adherence between the interlayer insulation film and the second metal wiring. The semiconductor device is provided with a stress buffer layer of which the elastic modulus is higher than that of the interlayer insulation film and is lower than that of the interlayer adhesion layer between the interlayer insulation film and the interlayer adhesion layer.

Abstract: A semiconductor device has an interlayer insulation film formed on a first metal wiring and formed of an organic compound having a lower dielectric constant than that of SiO2, a second metal wiring formed on the interlayer insulation film, and an interlayer adhesion layer to improve adherence between the interlayer insulation film and the second metal wiring. The semiconductor device is provided with a stress buffer layer of which the elastic modulus is higher than that of the interlayer insulation film and is lower than that of the interlayer adhesion layer between the interlayer insulation film and the interlayer adhesion layer.

Abstract: A semiconductor device has an interlayer insulation film formed on a first metal wiring and formed of an organic compound having a lower dielectric constant than that of SiO2, a second metal wiring formed on the interlayer insulation film, and an interlayer adhesion layer to improve adherence between the interlayer insulation film and the second metal wiring. The semiconductor device is provided with a stress buffer layer of which the elastic modulus is higher than that of the interlayer insulation film and is lower than that of the interlayer adhesion layer between the interlayer insulation film and the interlayer adhesion layer.

Abstract: In a hetero-junction bipolar transistor, an undoped Al0.7Ga0.3As stopper layer 5 having good etching controllability is provided on a base layer 4, thereby forming a base without etching damage, this resulting in achievement of the desired base resistance with good repeatability.

Abstract: The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.