Patents by Inventor Hiroshi Ariga

Hiroshi Ariga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9438147
    Abstract: The position detecting apparatus includes a comparing part that compares the value of the digital signal output from the AD converter and a reference value that is based on a preset reference amplitude at the timings and outputs a control signal responsive to a result of the comparison. The position detecting apparatus includes an amplitude controlling part that controls amplification factors of the first amplifier and the second amplifier in such a manner that the value of the digital signal output from the AD converter comes closer to the reference value in response to the control signal output from the comparing part.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ariga, Masahiro Inoue
  • Publication number: 20150015175
    Abstract: The position detecting apparatus includes a comparing part that compares the value of the digital signal output from the AD converter and a reference value that is based on a preset reference amplitude at the timings and outputs a control signal responsive to a result of the comparison. The position detecting apparatus includes an amplitude controlling part that controls amplification factors of the first amplifier and the second amplifier in such a manner that the value of the digital signal output from the AD converter comes closer to the reference value in response to the control signal output from the comparing part.
    Type: Application
    Filed: February 27, 2014
    Publication date: January 15, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Ariga, Masahiro Inoue
  • Patent number: 8922404
    Abstract: An aspect of one embodiment, there is provided a signal processor includes an AD-convertor outputting a conversion result and a conversion end flag, a second comparator configured to compare signal levels, a channel selection signal generation unit to select an input channel to input the AD-convertor, an direction identification flag generation unit to generate an direction identification flag, an edge signal generation unit to generate rising edges and lowering edges, an up-down counter to subject to be up or down on a count value in an output of each of edge signals, and an arithmetic processing unit to interlink the count value of the up-down counter and the conversion result of the AD-convertor to generate output data, wherein the arithmetic processing unit interpolates the count value of the up-down counter in the interlinking by using a correction value corresponding to a value of the direction identification flag in a period between an output of the edge signal and an output of the conversion end flag.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Ariga
  • Publication number: 20140354457
    Abstract: An aspect of one embodiment, there is provided a signal processor includes an AD-convertor outputting a conversion result and a conversion end flag, a second comparator configured to compare signal levels, a channel selection signal generation unit to select an input channel to input the AD-convertor, an direction identification flag generation unit to generate an direction identification flag, an edge signal generation unit to generate rising edges and lowering edges, an up-down counter to subject to be up or down on a count value in an output of each of edge signals, and an arithmetic processing unit to interlink the count value of the up-down counter and the conversion result of the AD-convertor to generate output data, wherein the arithmetic processing unit interpolates the count value of the up-down counter in the interlinking by using a correction value corresponding to a value of the direction identification flag in a period between an output of the edge signal and an output of the conversion end flag.
    Type: Application
    Filed: February 25, 2014
    Publication date: December 4, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Ariga
  • Patent number: 5271418
    Abstract: A brace for the ankle joint which comprises an outer cover for covering at least the ankle and a part of the lower leg, a pair of connection plates detachably attached to the inner surface of the outer cover at locations below the ankle by means of plane fasteners, and a pair of guard members which are to support the lower leg, and the lower ends of which are rotatably connected to the upper ends of the connection plates. The brace for the ankle joint is very safe, remarkably easy to use and provides an excellent fitness.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: December 21, 1993
    Assignee: Nippon Sigmax Co., Inc.
    Inventors: Noriyoshi Ohnuma, Daisaku Mukai, Hiroshi Ariga
  • Patent number: 4725926
    Abstract: An electric double layer capacitor utilizing an electric double layer formed by the interface of an electrolyte solution and polarizable electrodes, wherein the electrolyte solution comprises a quaternary phosphonium salt of the formula I dissolved in an organic solvent: ##STR1## wherein each of R.sub.1, R.sub.2, R.sub.3 and R.sub.4 is a hydrogen atom, an alkyl group having from 1 to 15 carbon atoms or an aryl group having from 6 to 15 carbon atoms, provided that not all of R.sub.1 to R.sub.4 are hydrogen atoms, and X is BF.sub.4, PF.sub.6 , ClO.sub.4, AsF.sub.6, SbF.sub.6, AlCl.sub.4 or R.sub.f SO.sub.3 wherein R.sub.f is a fluoroalkyl group having from 1 to 8 carbon atoms.
    Type: Grant
    Filed: January 15, 1987
    Date of Patent: February 16, 1988
    Assignees: Asahi Glass Company Ltd., Elna Company Ltd.
    Inventors: Takeshi Morimoto, Kazuya Hiratsuka, Yasuhiro Sanada, Hiroshi Ariga