Abstract: A differential amplifier circuit which enables oscillation of pre-scaler to prevent at the time no-signal causes sensitivity not to deteriorate to an AC signal itself. The differential amplifier circuit comprises a first pair of differential device consisting of transistors to which AC signal is inputted, load resistances, and a constant-current source, a second pair of differential device which is connected so as to perform positive feedback from terminals in between both ends of load resistances, and a capacitor for performing by-pass of AC signal of the terminals.

Abstract: In a flipflop circuit, each of master and slave latch/hold circuits is constituted of differential pairs consisting of transistors each connected between VCC and VSS without being in series with another transistor between VCC and VSS. A clock driving circuit has a pull-down function responding to a pair of complementary clocks so as to pull down the level of a pair of complementary data signals supplied to each latch/hold circuit. With this arrangement, the flipflop circuit composed of bipolar transistors can operate with a low voltage of not greater than 1 V.

Abstract: A radiocommunication system comprises an input/output stage section of the system, which includes a first and a second differential circuits each having a differential transistor pair and a current source for supplying operational current to each of the differential transistor pairs. The input pair of the first differential circuit is connected to the output pair of a transmitting section of the system to supply an output transmission signal through an antenna. The input of the second differential circuit is connected to the antenna and the output pair thereof are connected to the input pair of a receiving section of the system. Each of the current sources is implemented by a current mirror including a first transistor activated and inactivated by a changeover signal in a time shared control and a second transistor for supplying the operational current to a corresponding one of the differential transistor pairs.

Abstract: A clock driver circuit comprises a first driver including first and second inverters cascaded between an input terminal and a first output terminal for outputting a non-inverted signal delayed from the clock signal applied to the input terminal by a delay amount corresponding to two stages of inverters. The clock driver circuit also comprises and a second driver including third, fourth and fifth inverters cascaded between the input terminal and a second output terminal and a sixth inverter connected between the input terminal and the second output terminal. With this arrangement, a first signal delayed from the clock signal applied to the input terminal by a first delay amount corresponding to the third, fourth and fifth inverters, is synthesized by a wired-OR at the second output terminal with a second signal delayed from the clock signal applied to the input terminal by a second delay amount corresponding to the sixth inverter.

Abstract: A voltage-to-current converting circuit configured to convert an input voltage signal into a pair of complementary current signals by use of a current mirror, comprises a transistor 4 connected in the form of a diode and connected in series with a constant current source 21, a transistor 3 having a collector connector to a collector of the transistor 4, a transistor 2 having a base connected to a base of the transistor 3 so as to form a current mirror in cooperation with the transistor 3, the base of the transistor 2 being connected to receive an input voltage signal Vin, a bias circuit 5 for biasing the base of the transistors 3 and 2, and a transistor 1 having a base connected to a base of the transistor 4 so as to form a current mirror in cooperation with the transistor 4. The input voltage Vin is converted into a collector current I1 of the transistor 1 and a collector current I2 of the transistor 2.

Abstract: An amplifier circuit having an emitter-grounded amplifying stage formed of a transistor Q1 and a load resistor R.sub.L and having an output stage including an emitter follower formed of transistors Q2 and Q3. The base of the transistor Q1 of the amplifying stage and the base of the transistor Q3 of the output stage are connected with each other for receiving input signals and biased by a bias circuitry 5. The input signals thus given to the base of transistor Q3 for the emitter follower of the output stage cause the transistors Q2 and Q3 to alternately turn on and off to provide a higher output driving power to the load connected to the output terminal than prior art amplifier circuits having conventional emitter followers and resistor feedback amplification networks.

Abstract: A differential circuit comprises a differential stage responsive to input voltage levels in an ECL range for producing an output signal at an output node, a setting stage associated with the differential stage and responsive to a set signal in a CMOS range for setting the output node to a predetermined level, wherein a level-shift element is coupled between a bipolar transistor responsive to the set signal and the common emitter node of bipolar transistors responsive to the input voltage levels so that each bipolar transistor is prevented from destruction due to excess reverse bias voltage applied to the base node and the emitter node.

Abstract: A flip-flop circuit includes a hysteresis inverter, a data input terminal, a data output terminal, a clock input terminal and a transfer gate. The hysteresis inverter has a first inverter whose input and output nodes are connected respectively to the data input and output terminals, and a second inverter whose input and output node are connected respectively to the data output and input terminals. The transfer gate is connected between the data input and output terminals, and turns on and off in response to a clock signal applied to the clock input terminal, thereby changing hysteresis area or effects of the hysteresis inverter. The transfer gate causes the area of hysteresis to be variable, so that the circuit requires only a small number of gate stages, can operate at a high speed, and can operate at a low power supply voltage.

Abstract: A radio frequency amplifier comprises a differential amplifier having a pair of differential first and second transistors and a first and a second load resistor; an emitter grounded amplifier having a third transistor and a third load resistor; and a reference voltage generator having a constant-current source formed by a fourth transistor and a fourth load resistor. The emitter grounded amplifier receives a high frequency input signal and outputs a single signal output. One input node of the differential amplifier receives the output from the emitter grounded amplifier and the other input node receives a reference voltage from the reference voltage generator. The third and fourth transistors form a current-mirror circuit.

Abstract: An amplifier circuit has an amplifying transistor having its emitter directly grounded and a biasing transistor for supplying a bias current to the base of the amplifying transistor through its emitter. The biasing transistor receives at its base an output voltage generated and forwarded from a bias voltage generating circuit which is composed of a constant current source, a constant current transistor and another biasing transistor. One bias voltage generating circuit may provide its output voltage commonly to a plurality of biasing transistors each associated with the amplifying transistor. The circuit makes it possible to have the amplifying transistor operate at a desired operation point without using a resistor having a high resistance value. Further, since the emitter of the amplifying transistor is directly grounded, both the noise figure characteristics and high frequency characteristics are improved.

Abstract: A D/A converter includes a first resistor group connected between first and second reference potentials, a second resistor group consisting of resistors, first terminals of which are respectively connected between the first reference potential and a first node of a first resistor and other nodes in the first resistor group, an operational amplifier, first switching elements consisting of semiconductor elements each having an input electrode and two output electrodes, one of the output electrodes being connected to each second terminal in the second resistor group, and the other output electrode being connected to the non-inverting input terminal of the amplifier, second switching elements each consisting of a semiconductor element having an input electrode and two output electrodes, one of the output electrodes being connected to each second terminal in the second resistor group, and the other output electrode being connected to the inverting input terminal of the amplifier, and a drive circuit.

Abstract: A portable transceiver has a narrow band square microstrip antenna connected to a first radio receiver, a wideband sleeve or whip antenna connected to an associated duplexer, and a second radio receiver and a transmitter both connected to the wideband antenna via the duplexer. The square microstrip antenna if formed of a conductive emission plate and a conductive ground plate joined by a conductive connector plate. A housing enclosing the transceiver has an earphone and microphone set in its front side, the microstrip antenna under its back side, and the wideband sleeve or whip antenna mounted upright on its top side.

Abstract: A capacitor coupling usually delays response, especially during intermittent energization that provides a battery saving feature. The invention provides a feedback which retains charges stored on the capacitor during battery saving power off intervals and which gives an almost instantaneous response when power returns. An electronic switch in the feedback path controls the charge retention.

Abstract: In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected. Latch switches are inserted between the inverters and the corresponding data input terminals. Hold switches are inserted in the cross-connected portion of the two inverters. The latch switches are turned on/off in synchronism with a latch input while the hold switches are turned on/off in synchronism with a hold input.

Abstract: A bias circuit for an FET comprises a voltage divider having two potential points. A first of the potential points is connected to a gate of the FET. The other potential point is connected through a second FET which may be turned off or on to vary the potential at the first potential point in order to control the bias on the gate of the first FET. The switching of the second FET is controlled as a function of a threshold voltage between its gate and a voltage in the source-drain circuit of the second FET. In one embodiment, a diode feedback circuit may be used to provide the threshold current.

Abstract: A multistage type amplifier circuit comprises a plurality of FETs cascade-connected to each other through interstage capacitors. The first amplifier stage of an FET is additionally provided with a feedback circuit coupled between respective gates of the first-stage FET and the next stage FET. The next amplifier stage of an FET is also provided with a similar feedback circuit coupled between respective drains of the first and next stage FETs successively connected. Thus, this makes it possible to reduce the required number of dc block capacitors to less than one-half, resulting in a small area occupation of capacitors when IC is realized. Further, the amplifier circuit is configured so that each amplifier stage is not provided with a dc block capacitor in the negative feedback circuit, leading to a significant improvement in frequency characteristics of the amplifier circuit in a low frequency range.