Abstract: A pharmaceutical composition may be used in administering oxygen to a subject. The pharmaceutical composition may contain a perfluorocarbon dissolving oxygen therein. Further, a pharmaceutical composition may be used in decreasing the blood carbon dioxide partial pressure of a subject, and the pharmaceutical composition may contain a perfluorocarbon. Such a composition may be suitable for administered oral administration, nasogastric administration, trans-fistula gastric administration, or administration into a large intestine.

Abstract: A machine learning device includes: a generation unit generating a first shape model representing a shape of an object before deformation and a second shape model representing a shape of the object after the deformation based on measurement data before and after the deformation; and a learning unit learning a feature amount including a difference value between each micro region and another micro region that constitute the first shape model, and a relation providing a displacement from the each micro region of the first shape model to each corresponding micro region of the second shape model.

Abstract: A machine learning device includes: a generation unit generating a first shape model representing a shape of an object before deformation and a second shape model representing a shape of the object after the deformation based on measurement data before and after the deformation; and a learning unit learning a feature amount including a difference value between each micro region and another micro region that constitute the first shape model, and a relation providing a displacement from the each micro region of the first shape model to each corresponding micro region of the second shape model.

Abstract: A fault diagnosis method utilizing a fault diagnosis system for diagnosing a photovoltaic module by estimating a fault location, the fault diagnosis system including a signal generator for generating and inputting an input signal into a positive terminal or a negative terminal of the photovoltaic module, a waveform observer for observing a reflected output signal from an open end or the fault location, a diagnosis unit for estimating the fault location based on the output signal, a conductive body, and an alignment unit for controlling the positions of the conductive body and/or the photovoltaic module. The diagnosis method includes controlling the positions of the conductive body and/or the photovoltaic module, observing the output signal of the input signal, and estimating the fault location based on two reflected output signals of input signals inputted into the positive terminal and the negative terminal of the photovoltaic module.

Abstract: A fault diagnosis method utilizing a fault diagnosis system for diagnosing a photovoltaic module by estimating a fault location, the fault diagnosis system including a signal generator for generating and inputting an input signal into a positive terminal or a negative terminal of the photovoltaic module, a waveform observer for observing a reflected output signal from an open end or the fault location, a diagnosis unit for estimating the fault location based on the output signal, a conductive body, and an alignment unit for controlling the positions of the conductive body and/or the photovoltaic module. The diagnosis method includes controlling the positions of the conductive body and/or the photovoltaic module, observing the output signal of the input signal, and estimating the fault location based on two reflected output signals of input signals inputted into the positive terminal and the negative terminal of the photovoltaic module.

Abstract: Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Abstract: Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube.

Abstract: Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

Abstract: A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

Abstract: Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution.

Abstract: Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution.

Abstract: Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube.

Abstract: Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Abstract: A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set 216 for a logic circuit includes a target vector identification unit 204 identifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set 216, and a test vector set conversion unit 206 converting the test vector identified by the test vector identification unit 204 and to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

Abstract: The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.

Abstract: Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device 400 converts a test vector set corresponding to the full scan sequential circuit. The conversion device 400 comprises a setting unit 402 for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit 404 for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit 402.

Abstract: A message sending and reception optimizing method using a sender's end information processing apparatus disposed on a sender's end of a message and a recipient's end information processing apparatus disposed on a recipient's end of the message has a step of determining an optimum form of message sending and reception while considering convenience of a sender and/or a recipient by communicating predetermined information between the sender's end information processing apparatus and the recipient's end information processing apparatus before performance of the message sending and reception.

Abstract: The customer information utilization system of the present invention includes history acquisition units, history storage units, and history utilization units. The history acquisition units are arranged in each device belonging to users and acquire history information relating to the history of use of the devices. The history storage units collect history information relating to the history of use of each device belonging to the users by way of the history acquisition units and store the history information. When a product or service is to be provided or when an application is to be executed, the history utilization units use appropriate history information of the history information relating to the history of use of each device belonging to the users to produce customer information that is to be utilized in the product, service or application.

Abstract: In a strongly testable DFT method, the length of a test sequence is reduced, thereby reducing the amount of circuitry to be added for testing purposes. Test plans, generated one for each of circuit elements forming a data path, are scheduled in parallel in a form that can be compacted, and a compaction operation is applied to generate a compacted test plan. The test sequence is generated by inserting the test patterns needed for each circuit element into the compacted test plan.

Abstract: The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.