Patents by Inventor Hiroshi Dohji

Hiroshi Dohji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory testing using multiple processor unit, DMA, and SIMD instruction
    Patent number: 8181072
    Abstract: To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS).
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Dohji, Hironori Makimura, Minoru Kida, Nobuyoshi Tanaka
  • EFFECTIVE METHOD TO PERFORM MEMORY TEST USING MULTIPLE PROCESSOR UNIT, DMA, AND SIMD INSTRUCTION
    Publication number: 20090187793
    Abstract: To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS).
    Type: Application
    Filed: January 21, 2009
    Publication date: July 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hiroshi Dohji, Hironori Makimura, Minoru Kida, Nobuyoshi Tanaka
  • Method to determine dynamic compilation time and to select bytecode execution mode
    Patent number: 6546550
    Abstract: To perform efficient execution of a bytecode by combining an interpreter and a compiler. At a time of a bytecode execution by an interpreter, if an instruction to be executed is a backward conditional branch instruction, it is determined whether the backward conditional branch instruction is a back edge of a loop. And if it is determined the instruction is a back edge of a loop, the number of the loop iteration is estimated and stored into a storage. A bytecode execution mode is selected according to the estimated number of the loop iteration. This execution mode comprises the modes of immediately compiling a method including a loop, and having the interpreter execute a bytecode.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 8, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kazunori Ogata, Hideaki Komatsu, Hiroshi Dohji