Patents by Inventor Hiroshi Fujimura

Hiroshi Fujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180277109
    Abstract: According to one embodiment, an edit assisting system includes a server device and a client device. The client device displays a first object, which indicates first speech of a user and a first portion of the first speech, and a second object, which indicates second speech generated by the server device and a second portion of the second speech, on a screen based on a scenario indicated in scenario data. The first and second portions are editable. The client device transmits edit data indicating the first portion which is edited and/or the second portion which is edited to the server device. The server device rewrites the scenario data by changing the first portion of the first speech and/or the second portion of the second speech is the scenario by using the edit data.
    Type: Application
    Filed: August 30, 2017
    Publication date: September 27, 2018
    Inventors: Hiroshi Fujimura, Kenji Iwata
  • Publication number: 20180277106
    Abstract: According to an embodiment, a verification system includes a storage controller, first and second receivers, a comparator, a response constructor, a response generator, and an output controller. The storage controller stores, in a storage, first response data and first situation data associated with the first response data. The first receiver receives second response data. The comparator determines a similarity between second situation data indicating a second context for using the second response data and the first situation data. The response constructor constructs response content information comprising the second response data and the first response data associated with the first situation data having the similarity equal to or greater than a threshold. The second receiver receives speech data. The response generator generates a response sentence corresponding to the speech data using the response content information. The output controller outputs for display one or more response sentences.
    Type: Application
    Filed: August 28, 2017
    Publication date: September 27, 2018
    Inventors: Takami YOSHIDA, Kenji IWATA, Hiroshi FUJIMURA
  • Publication number: 20180279010
    Abstract: According to an embodiment, an information processing apparatus includes one or more processors. The one or more processors are configured to acquire target sentence data including a plurality of morphemes obtained by speech recognition and speech generation time of each morpheme from the plurality of morphemes; and assign display time according to a difference between a confirmed sentence of which a user's correction for the target sentence data is confirmed and a second confirmed sentence of a previous speech generation time.
    Type: Application
    Filed: August 22, 2017
    Publication date: September 27, 2018
    Inventors: Nayuko WATANABE, Kosei FUME, Hiroshi FUJIMURA
  • Publication number: 20180268809
    Abstract: According to one embodiment, a voice keyword detection apparatus includes a memory and a circuit coupled with the memory. The circuit calculates a first score for a first sub-keyword and a second score for a second sub-keyword. The circuit detects the first and second sub-keywords based on the first and second scores. The circuit determines, when the first sub-keyword is detected from one or more first frames, to accept the first sub-keyword. The circuit determines, when the second sub-keyword is detected from one or more second frames, whether to accept the second sub-keyword based on a start time and/or an end time of the one or more first frames and a start time and/or an end time of the one or more second frames.
    Type: Application
    Filed: August 30, 2017
    Publication date: September 20, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi FUJIMURA
  • Publication number: 20180258508
    Abstract: A grain-oriented electrical steel sheet includes: a chemical composition represented by, in mass %, Si: 2.0% to 5.0%, Mn: 0.03% to 0.12%, Cu: 0.10% to 1.00%, sb or Sn, or both thereof: 0.000% to 0.3% in total, Cr: 0% to 0.3%, P: 0% to 0.5%, Ni: 0% to 1%, and the balance: Fe and impurities, in which an L-direction average diameter of crystal grains observed on a surface of the steel sheet in an L direction parallel to a rolling direction is equal to or more than 3.0 times a C-direction average diameter in a C direction vertical to the rolling direction.
    Type: Application
    Filed: September 28, 2016
    Publication date: September 13, 2018
    Applicant: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Hiroshi FUJIMURA, Fumiaki TAKAHASHI, Takashi KATAOKA
  • Publication number: 20180197464
    Abstract: A drive circuit having an output terminal includes a buffer circuit including a first transistor and a second transistor that are connected in parallel between a power supply and the output terminal. The first transistor and the second transistor are controlled such that after the first transistor and the second transistor are simultaneously turned on, the second transistor is turned off earlier than the first transistor.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Applicant: JOLED INC.
    Inventors: Tetsuro YAMAMOTO, Hiroshi FUJIMURA
  • Patent number: 9984627
    Abstract: A display panel includes a plurality of pixels, and a plurality of signal lines and a plurality of power lines. The plurality of pixels are disposed in matrix. The plurality of signal lines and the plurality of power lines both extend in a column direction. The plurality of power lines include a plurality of first power lines assigned to respective odd-numbered pixel rows and a plurality of second power lines assigned to respective even-numbered pixel rows. The first power lines are electrically coupled to one another. The second power lines are electrically coupled to one another.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 29, 2018
    Assignee: JOLED Inc.
    Inventors: Hiroshi Fujimura, Tetsuro Yamamoto
  • Publication number: 20180137863
    Abstract: According to an embodiment, a speech recognition apparatus includes a calculation unit that calculates, based on a speech signal, a score vector sequence including score vectors including an acoustic score for each of input symbols, a search unit that generates an input symbol string by searching for a path of the input symbol tracing the acoustic score having a high likelihood in the score vector sequence and that generates an output symbol representing a recognition result of the speech signal based on a recognition target symbol representing linguistic information as a recognition target among the input symbols, an additional symbol acquisition unit that obtains an additional symbol representing paralinguistic information and/or non-linguistic information from among the input symbols included in a range corresponding to the output symbol, and an output unit that outputs the output symbol and the obtained additional symbol in association with each other.
    Type: Application
    Filed: August 25, 2017
    Publication date: May 17, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Manabu NAGAO, Hiroshi FUJIMURA
  • Publication number: 20180082688
    Abstract: According to an embodiment, a conference support system includes a recognizer, a classifier, a first caption controller, a second caption controller, and a display controller. The recognizer is configured to recognize text data corresponding speech from a speech section and configured to distinguish between the speech section and a non-speech section in speech data. The classifier is configured to classify the text data into first utterance data representing a principal utterance and second utterance data representing another utterance. The first caption controller is configured to generate first caption data for displaying the first utterance data without waiting for identification of the first utterance data to finish. The second caption controller is configured to generate second caption data for displaying the second utterance data after identification of the second utterance data finishes. The display controller is configured to control a display of the first caption data and the second caption data.
    Type: Application
    Filed: February 23, 2017
    Publication date: March 22, 2018
    Inventors: Taira ASHIKAWA, Kosei FUME, Masayuki ASHIKAWA, Hiroshi FUJIMURA
  • Publication number: 20180075839
    Abstract: A correction system of the embodiment includes an interface system, a calculator, a generator, and a display controller. The interface system receives correction information for correcting a voice recognition result. The calculator estimates a part of the voice recognition result to be corrected and calculates a degree of association between the part to be corrected and the correction information. The generator generates corrected display information comprising at least one of the correction information and the part to be corrected using a display format corresponding to the degree of association. The display controller outputs the corrected display information on a display.
    Type: Application
    Filed: February 23, 2017
    Publication date: March 15, 2018
    Inventors: Kosei FUME, Taira ASHIKAWA, Masayuki ASHIKAWA, Hiroshi FUJIMURA
  • Publication number: 20170092197
    Abstract: A display panel includes a plurality of pixels, and a plurality of signal lines and a plurality of power lines. The plurality of pixels are disposed in matrix. The plurality of signal lines and the plurality of power lines both extend in a column direction. The plurality of power lines include a plurality of first power lines assigned to respective odd-numbered pixel rows and a plurality of second power lines assigned to respective even-numbered pixel rows. The first power lines are electrically coupled to one another. The second power lines are electrically coupled to one another.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 30, 2017
    Inventors: Hiroshi Fujimura, Tetsuro Yamamoto
  • Patent number: 9595261
    Abstract: According to an embodiment, a pattern recognition device includes a signal processor, a first recognizer, a detector, and a second recognizer. The signal processor is configured to calculate a feature of a time-series signal for each frame. The first recognizer is configured to recognize which of a leaf class and a single class of a first class group the time-series signal belongs to for each frame based on the feature and output a recognition result. The detector is configured to detect a segment including a first target class on the basis of a sum of probabilities of the leaf classes which the frame belongs to on the basis of the recognition results for each frame. The second recognizer is configured to recognize which of second target classes the segment belongs to on the basis of the recognition results for the frames within the segment.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Fujimura
  • Publication number: 20170061879
    Abstract: A register circuit includes an output circuit and an input circuit. The output circuit includes a first transistor and a second transistor. The first transistor is provided in a first electrically-conductive path between a first control terminal and an output terminal. The second transistor is provided in a second electrically-conductive path between a first power terminal and the output terminal. The input circuit includes a third transistor and a fourth transistor. The third transistor is provided in a third electrically-conductive path between an input terminal and a gate terminal of the first transistor. The fourth transistor is provided in a fourth electrically-conductive path between a second control terminal and a gate terminal of the third transistor and has a gate terminal that is coupled to the input terminal.
    Type: Application
    Filed: August 9, 2016
    Publication date: March 2, 2017
    Inventor: Hiroshi Fujimura
  • Publication number: 20160379624
    Abstract: According to an embodiment, a speech recognition result output device includes a storage and processing circuitry. The storage is configured to store a language model, for speech recognition. The processing circuitry is coupled to the storage and configured to acquire a phonetic sequence, convert the phonetic sequence into a phonetic sequence feature vector, convert the phonetic sequence feature vector into graphemes using the language model, and output the graphemes.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi FUJIMURA
  • Patent number: 9508781
    Abstract: A method for manufacturing an organic electroluminescence display including multilayer structures that are each formed in a respective one of pixel areas in an effective area of a substrate and are each formed by a lower electrode, an organic layer, and an upper electrode, the organic electroluminescence display having a common electrode that electrically connects the pixel areas, the method including the steps of: forming a protective electrode and an outer-peripheral electrode that are electrically connected to the common electrode; forming the multilayer structures; and carrying out film deposition treatment involving electrification of the substrate.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: November 29, 2016
    Assignee: JOLED INC.
    Inventors: Hiroshi Fujimura, Mitsuru Asano, Toshiaki Imai
  • Publication number: 20160329394
    Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 10, 2016
    Inventors: Mitsuru Asano, Seiichiro Jinta, Masatsugu Tomida, Hiroshi Fujimura
  • Publication number: 20160275394
    Abstract: According to an embodiment, an arithmetic operation apparatus for a neural network includes an input layer calculator, a correction unit calculator, a hidden layer calculator, and an output layer calculator. The input layer calculator is configured to convert an input pattern into features as outputs of an input layer. The correction unit calculator is configured to perform calculation on N unit groups corresponding respectively to N classes of the input pattern and including correction units that each multiply a value based on inputs by a weight determined for the corresponding class. The hidden layer calculator is configured to perform calculation in a hidden layer based on the outputs of the input layer, another hidden layer, or the correction unit calculator. The output layer calculator is configured to perform calculation in an output layer based on the calculation for the hidden layer or the outputs of the correction unit calculator.
    Type: Application
    Filed: March 15, 2016
    Publication date: September 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi FUJIMURA, Takashi MASUKO
  • Patent number: 9330662
    Abstract: According to an embodiment, a pattern classifier device includes a decision unit, an execution unit, a calculator, and a determination unit. The decision unit is configured to decide a subclass to which the input pattern is to belong, based on attribute information of the input pattern. The execution unit is configured to determine whether the input pattern belongs to a class that is divided into subclasses, using a weak classifier allocated to the decided subclass, and output a result of the determination and a reliability of the weak classifier. The calculator is configured to calculate an integrated value obtained by integrating an evaluation value based on the determination result and the reliability. The determination unit is configured to repeat the determination processing when a termination condition of the determination processing is not satisfied, and terminate the determination processing and output the integrated value when the termination condition, has been satisfied.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 3, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Fujimura, Takashi Masuko
  • Publication number: 20150279872
    Abstract: Provided is a display device provided with a substrate and a display element on the substrate, the substrate including: a base; and a plurality of capacitive elements that are stacked on the base and each include a bottom electrode and a top electrode, wherein the plurality of capacitive elements include a lower capacitive element and an upper capacitive element that are different in position in a stacking direction, and the bottom electrode of the lower capacitive element and the top electrode of the upper capacitive element are electrically independent from one another.
    Type: Application
    Filed: March 12, 2015
    Publication date: October 1, 2015
    Inventors: Yuichi Kato, Yasuhiro Terai, Hiroshi Fujimura
  • Patent number: 9147133
    Abstract: A pattern recognition device includes a feature vector calculator; a model selecting unit; a correction vector calculator; a feature vector correcting unit; and a pattern recognition unit. The correction vector calculator calculates, for each of the selection models, a modified directional vector having N dimensional components (N?1). A value of the n-th dimensional component (N?n?1) of the modified directional vector is obtained by subtracting a value of the n-th dimensional component of the variance vector multiplied by a predetermined coefficient from an absolute value of the n-th component of a different vector between the average vector and feature vectors to obtain a first value, and then multiplying the first value by a plus or minus sign identical to a sign of the n-th dimensional component of the difference vector, and further calculate a correction vector with respect to a vector obtained by superimposing the modified directional vectors.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: September 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Fujimura