Patents by Inventor Hiroshi Fukiage

Hiroshi Fukiage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test system and manufacturing of semiconductor device
    Publication number: 20040175850
    Abstract: A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
    Type: Application
    Filed: March 15, 2004
    Publication date: September 9, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Isao Shimizu, Masayuki Sato, Hiroshi Fukiage
  • Test system and manufacturing of semiconductor device
    Patent number: 6727723
    Abstract: A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: April 27, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Isao Shimizu, Masayuki Sato, Hiroshi Fukiage
  • Test system and manufacturing of semiconductor device
    Publication number: 20020171449
    Abstract: A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 21, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Isao Shimizu, Masayuki Sato, Hiroshi Fukiage
  • Semiconductor integrated circuit and method of checking memory
    Patent number: 6467056
    Abstract: A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Satou, Isao Shimizu, Hiroshi Fukiage
  • Test system and manufacturing of semiconductor device
    Patent number: 6400173
    Abstract: A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Isao Shimizu, Masayuki Sato, Hiroshi Fukiage
  • Semiconductor integrated circuit and method for testing memory
    Patent number: 6233182
    Abstract: A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determining the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: May 15, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Satou, Isao Shimizu, Hiroshi Fukiage