Patents by Inventor Hiroshi Funakura
Hiroshi Funakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952497Abstract: An object of the present invention is to provide a phycocyanin pigment composition insoluble in water and provide food, cosmetics, a coating material or a printing marker for pharmaceuticals or agricultural chemicals, a stationery product, a writing tool, a printing ink, an inkjet ink, a metal ink, a paint, a plastic coloring agent, a color toner, a fluorescent labeling agent, a fluorescent probe, or a chemical sensor, each containing the pigment composition. It was found that the phycocyanin pigment composition containing phycocyanin and a metal or a metal compound was insoluble in water, and thus the present invention was accomplished.Type: GrantFiled: March 18, 2021Date of Patent: April 9, 2024Assignee: DIC CORPORATIONInventors: Seiji Funakura, Takashi Shibano, Hiroshi Sekikawa
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Patent number: 7148529Abstract: A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light from passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.Type: GrantFiled: March 20, 2002Date of Patent: December 12, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Oida, Masatoshi Fukuda, Yasuhiro Koshio, Hiroshi Funakura
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Patent number: 6960494Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: October 21, 2004Date of Patent: November 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20050051810Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: October 21, 2004Publication date: March 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Patent number: 6836012Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: March 29, 2002Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Patent number: 6469373Abstract: In a semiconductor apparatus comprising a semiconductor chip, a wiring substrate having the semiconductor chip mounted thereon, an under-fill resin sheet interposed between the semiconductor chip and the wiring substrate, and a resin sealing body for sealing the semiconductor chip, the under-fill resin sheet and the wiring substrate, the under-fill resin sheet is greater than the semiconductor chip in size, and its end is exposed from at least one side face of the resin sealing body. Since an end of the under-fill resin sheet is exposed from at least one side face of the resin sealing body, then the water contained in the under-fill resin sheet escapes from an exposed end of the under-fill resin sheet to the outside of the resin sealing body, thus making it possible to improve re-flow resistance of the semiconductor apparatus.Type: GrantFiled: May 15, 2001Date of Patent: October 22, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi
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Publication number: 20020140062Abstract: A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light fiom passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.Type: ApplicationFiled: March 20, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBA.Inventors: Mitsuru Oida, Masatoshi Fukuda, Yasuhiro Koshio, Hiroshi Funakura
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Publication number: 20020140095Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: March 29, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20010040280Abstract: In a semiconductor apparatus comprising a semiconductor chip, a wiring substrate having the semiconductor chip mounted thereon, an under-fill resin sheet interposed between the semiconductor chip and the wiring substrate, and a resin sealing body for sealing the semiconductor chip, the under-fill resin sheet and the wiring substrate, the under-fill resin sheet is greater than the semiconductor chip in size, and its end is exposed from at least one side face of the resin sealing body. Since an end of the under-fill resin sheet is exposed from at least one side face of the resin sealing body, then the water contained in the under-fill resin sheet escapes from an exposed end of the under-fill resin sheet to the outside of the resin sealing body, thus making it possible to improve re-flow resistance of the semiconductor apparatus.Type: ApplicationFiled: May 15, 2001Publication date: November 15, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi