Abstract: A signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. A local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits and determines which of the second local bus, first local bus, and system bus will be connected to the local memory bus.

Abstract: The invention incorporates a signal processing circuit having a data input-output (I/O) circuit, a microprocessor, a dedicated processing circuit, a local memory, and a memory access control circuit interconnected over a bus. The bus includes a system bus and a local memory bus. The system bus connects to the data I/O circuit, microprocessor, dedicated processing circuit, and memory access control circuit. The local memory bus connects to the local memory. First, second, and third connection circuits connect between the system bus and local memory bus, between a first local bus in the dedicated processing circuit and the local memory bus, and between a second local bus in the data I/O circuit and the local memory bus. The memory access control circuit controls the first, second, and third connection circuits according to priorities assigned for the connection circuits. The system bus transfers control information among the data I/O circuit, dedicated processing circuit, and memory access control.

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.

Abstract: There is disclosed a method and apparatus for detecting motion by a video encoder. The method starts with dividing a target block whose motion is to be detected into blocks at different pixel positions. A reference image block is extracted from a reference image. The degrees of similarity of the blocks to the reference image block are simultaneously calculated by a calculating unit. A block having the highest degree of similarity is determined, based on their degrees of similarity. A vector corresponding to the determined block is taken as a motion vector representing the block.

Abstract: It is an object of the present invention to provide a security system and security apparatus with excellent user-friendliness. A receiver 5 acquires the phone number of a cellular phone carried by a visitor, the transfer function unit 204 checks the phone number thus acquired against the phone number of an anticipated visitor to identify the visitor, and transfers the information to a personal digital assistant (PDA) unit to be redirected if the transfer is judged to be necessary.

Abstract: A semiconductor integrated circuit includes a single instruction multiple data (SIMD) unit conducting a concurrent operation for a plurality of data items, a data buffer connectable to the SIMD unit, and a data transfer control unit for controlling transfer of data for the data buffer thereby, the data transfer control unit controls the transfer of data for a subsequent operation to the buffer in concurrence with the operation of the SIMD unit for the plural data items read from the data buffer and in concurrent with the operation of the SIMD unit, data for a subsequent operation is transferred to the data buffer.

Abstract: A data processing system used for a net-order sale or the like includes a host apparatus connectable to a terminal apparatus via a network. The host apparatus includes a database in which cryptographic keys are registered in being caused to correspond to user IDs. The cryptographic keys are caused to be related in a one-to-one manner to appliance manufacture numbers of domestic electrical apparatuses onto which terminal apparatuses are integrated. The host apparatus retrieves, from the database, a cryptographic key corresponding to a user ID that accompanies a transaction request from the terminal apparatus. Using the retrieved cryptographic key, the host apparatus performs encryption/decryption processings of information data transmitted/received between the terminal apparatus and the host apparatus. Information having a one-to-one correspondence relationship with the appliance manufacture number of the domestic electrical apparatus is utilized as the whole of the cryptographic key.

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches which supply power to the logic circuit block, and a switch control circuit which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with a clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed.

Abstract: The present invention includes a logic circuit block (8) operated in synchronism with a clock signal, power supply switches (12, 14) which supply power supplies to the logic circuit block, and a switch control circuit (2) which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with the clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed.

Abstract: There is disclosed a method and apparatus for detecting motion by a video encoder. The method starts with dividing a target block whose motion is to be detected into blocks at different pixel positions. A reference image block is extracted from a reference image. The degrees of similarity of the blocks to the reference image block are simultaneously calculated by a calculating unit. A block having the highest degree of similarity is determined, based on their degrees of similarity. A vector corresponding to the determined block is taken as a motion vector representing the block.

Abstract: There is disclosed a method and apparatus for detecting motion by a video encoder. The method starts with dividing a target block whose motion is to be detected into blocks at different pixel positions. A reference image block is extracted from a reference image. The degrees of similarity of the blocks to the reference image block are simultaneously calculated by a calculating unit. A block having the highest degree of similarity is determined, based on their degrees of similarity. A vector corresponding to the determined block is taken as a motion vector representing the block.

Abstract: An analog to digital converter capable of compensating characteristic unevenness of a signal amplification unit provided at a foregoing part of an analog to digital conversion unit and a signal conversion apparatus using the analog to digital converter are disclosed. An input signal is inputted to an analog to digital conversion unit after being converted from a first physical quantity into a second physical quantity by a signal processing unit. Further, a standard signal is converted from the first physical quantity into the second physical quantity by another or the same processing unit having the same function and is inputted to the analog to digital conversion unit. In the analog to digital conversion unit, analog to digital conversion is performed using the standard signal converted into this second physical quantity.