Abstract: A clock recovery circuit is provided with an STC counter, an adder for setting the initial value of the STC counter by adding the value of a PCR and the multiplexing delay time; a subtracter for subtracting the multiplexing delay time from the output of the STC counter; a latched STC register for latching the subtraction result of the subtracter; a PCR register for latching the value of the PCR; and a PWM for controlling the frequency of an external clock oscillation source that supplies a clock signal to the STC counter. The clock oscillation source is provided with an LPF and a VCO, wherein a clock signal outputted from the VCO is supplied to the STC counter and a timer within a stream multiplexing circuit. The clock signal outputted from the clock oscillation source is a reference clock signal of an MPEG system. Thereby, the scale of the entire device can be reduced by reducing the number of separation and decoding circuits.

Abstract: A clock recovery circuit is provided with an STC counter, an adder for setting the initial value of the STC counter by adding the value of a PCR and the multiplexing delay time; a subtracter for subtracting the multiplexing delay time from the output of the STC counter; a latched STC register for latching the subtraction result of the subtracter; a PCR register for latching the value of the PCR; and a PWM for controlling the frequency of an external clock oscillation source that supplies a clock signal to the STC counter. The clock oscillation source is provided with an LPF and a VCO, wherein a clock signal outputted from the VCO is supplied to the STC counter and a timer within a stream multiplexing circuit. The clock signal outputted from the clock oscillation source is a reference clock signal of an MPEG system. Thereby, the scale of the entire device can be reduced by reducing the number of separation and decoding circuits.

Abstract: In a recording system for digital broadcasting are provided a log data generation unit for generating log data (a log) based on information about TS packets outputted from a packet separation unit, a data filter unit and a data search unit. The log is comprised of, for example, the first to fourth 4-byte words. The log is generated with respect to each TS packet that has passed through the packet separation unit and temporarily stored in a register within the log data generation unit. Thereafter, when the content of the stored log satisfies previously determined conditions, the log data generation unit outputs the log to a memory access unit (control unit).

Abstract: A fault simulator comprises a storage for storing a truth table that is a fault model, a simulation executing unit for executing a simulation on the basis of a given signal pattern by the use of the truth table stored in the storage, a simulation result judging unit for analyzing a result of the simulation by the simulation executing unit and judging whether a fault in a circuit to be inspected can be detected by the signal pattern, and a judgment result output device for displaying a judgment result by the simulation result judging unit, characterized in that the truth table stored in the storage is created in such a way as to reflect a fault of an internal circuit in a block realizing one function forming the semiconductor integrated circuit, the fault making the output of the block high impedance.