Patents by Inventor Hiroshi Ibuka

Hiroshi Ibuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8710915
    Abstract: An apparatus, includes a plurality of circuits each of which operates with a reference voltage, a constant current generator which generates a substantially constant current, and distributes the substantially constant current to each of the circuits, and a plurality of converters, each of the converters respectively corresponding to each of the circuits, each of which converts the substantially constant current to the reference voltage and respectively provides the reference voltage to each of the circuits.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: April 29, 2014
    Assignee: NEC Corporation
    Inventor: Hiroshi Ibuka
  • Patent number: 7759992
    Abstract: A clock distribution circuit according to an exemplary aspect of the present invention comprises a drive power boost signal generator which generates and outputs a drive power boost signal, and a CML circuit which outputs a first signal combined by a second signal when the drive power boost signal indicates active state and outputs the first signal when the drive power boost signal indicates an inactive state.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: July 20, 2010
    Assignee: NEC Corporation
    Inventor: Hiroshi Ibuka
  • Publication number: 20090051416
    Abstract: An apparatus, includes a plurality of circuits each of which operates with a reference voltage, a constant current generator which generates a substantially constant current, and distributes the substantially constant current to each of the circuits, and a plurality of converters, each of the converters respectively corresponding to each of the circuits, each of which converts the substantially constant current to the reference voltage and respectively provides the reference voltage to each of the circuits.
    Type: Application
    Filed: July 14, 2008
    Publication date: February 26, 2009
    Applicant: NEC CORPORATION
    Inventor: Hiroshi Ibuka
  • Publication number: 20070229131
    Abstract: A clock distribution circuit according to an exemplary aspect of the present invention comprises a drive power boost signal generator which generates and outputs a drive power boost signal, and a CML circuit which outputs a first signal combined by a second signal when the drive power boost signal indicates active state and outputs the first signal when the drive power boost signal indicates an inactive state.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 4, 2007
    Applicant: NEC CORPORATION
    Inventor: Hiroshi Ibuka
  • Patent number: 7005907
    Abstract: In an integrated circuit device, a clock signal distribution section is arranged in an outer circumferential area of a semiconductor chip to supply a clock signal. Each of interface circuit blocks has at least an internal circuit operating based on the clock signal supplied from the clock signal distribution section.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: February 28, 2006
    Assignee: NEC Corporation
    Inventor: Hiroshi Ibuka
  • Publication number: 20030231043
    Abstract: In an integrated circuit device, a clock signal distribution section is arranged in an outer circumferential area of a semiconductor chip to supply a clock signal. Each of interface circuit blocks has at least an internal circuit operating based on the clock signal supplied from the clock signal distribution section.
    Type: Application
    Filed: June 11, 2003
    Publication date: December 18, 2003
    Applicant: NEC Corporation
    Inventor: Hiroshi Ibuka