Abstract: The present invention provides a package substrate which comprises a substrate defined by top and bottom surfaces and having a plurality of perforations; a resin insulation layer configured to implement a multi-level structure disposed on both surfaces of the substrate; a built-up wiring layer implementing the multi-level structure disposed on the resin insulation layer on both surfaces of the substrate; and a semiconductor chip mounting region provided on the top or the bottom surface of the substrate; wherein, a perforation exists on any straight line connecting from the center of the substrate to an arbitrary point on a periphery of the substrate.

Abstract: A wiring substrate provides an inner wiring substrate having through hole portions. On at least one main surface of the inner wiring substrate, a plurality of build up layers are laminated. The build up layers have a stacked via, for example, as a power source system via. The stacked via is formed by stacking the vias in multiple steps to form a straight line. The stacked via has a large diameter via which is larger than other via constituting the stacked via, or is constituted of large diameter vias larger than other via in the same build up layer.

Abstract: The present invention provides a package substrate which comprises a substrate defined by top and bottom surfaces and having a plurality of perforations; a resin insulation layer configured to implement a multi-level structure disposed on both surfaces of the substrate; a built-up wiring layer implementing the multi-level structure disposed on the resin insulation layer on both surfaces of the substrate; and a semiconductor chip mounting region provided on the top or the bottom surface of the substrate; wherein, a perforation exists on any straight line connecting from the center of the substrate to an arbitrary point on a periphery of the substrate.