Patents by Inventor Hiroshi Ikegaya

Hiroshi Ikegaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080188376
    Abstract: According to the present invention, a means of estimating the place of origin of a test subject by quickly and conveniently determining the genome type of JC virus infecting a test subject is provided. The present invention relates to a set of oligonucleotide probes for determining the genome type of JC virus infecting a test subject, such set containing: oligonucleotide probes (a-1) and (a-2); oligonucleotide probes (b-1) and (b-2); oligonucleotide probes (c-1) and (c-2); oligonucleotide probes (d-1), (d-2), (d-3), and (d-4); oligonucleotide probes (e-1), (e-2), and (e-3); oligonucleotide probes (f-1), (f-1), and (f-3); oligonucleotide probes (g-1), (g-2), and (g-3); oligonucleotide probes (h-1), (h-2), (h-3), and (h-4); oligonucleotide probes (i-1) and (i-2); oligonucleotide probes (j-1), (j-2), and (j-3); oligonucleotide probes (k-1), (k-2), and (k-3); and oligonucleotide probes (l-1) and (l-2).
    Type: Application
    Filed: December 5, 2007
    Publication date: August 7, 2008
    Applicants: Toyo Kohan Co., Ltd., National Research Institute of Police Science
    Inventors: Hiroshi Ikegaya, Koichi Sakurada, Koichi Hirayama, Kenji Isogai
  • Patent number: 5437016
    Abstract: An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a multi-processor field of a translation lookaside buffer (TLB) has a value indicating whether or not the entry corresponds to an area common among virtual processors. The MP field of the TLB is compared with contents of the multi-processor register, and a virtual processor field of the TLB is compared with contents of a virtual processor register. If the value coincides with the multi-processor field or if the value does not coincide with the multi-processor field and the value coincides with the virtual processor field, contents of an absolute address field of the TLB are input to an absolute address register. This increases the effective capacity and utilization of the TLB to avoid decreasing of performance of the virtual machines.
    Type: Grant
    Filed: July 6, 1992
    Date of Patent: July 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ikegaya, Hidenori Umeno, Tsuyoshi Watanabe
  • Patent number: 4802084
    Abstract: In order to carry out address translation which can reduce an overhead of the VMCP to support a virtual storage, a flag indicating a common segment in the virtual machine and a system identifier are held in a TLB, and a VM identifier is held in a segment table origin stack. For the common segment, a current VM identifier is compared with the VM identifier in the segment table origin stack to determine validity of a TLB entry, and for a non-common segment, a system identifier read from the segment table origin stack is compared with the system identifier in the TLB entry to determine validity of the TLB entry.
    Type: Grant
    Filed: February 10, 1986
    Date of Patent: January 31, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Ikegaya, Hidenori Umeno, Takashige Kubo, Yoshio Ukai, Nobuyoshi Sugama