Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Abstract: The invention provides a warp printer, a weaving machine and a weaving method each having high freedom of a pattern to be expressed on a woven fabric and versatility to cope with production of woven fabrics of various kinds in limited quantities. A warp printer 1 includes yarn width reducing means 4 for reducing a width of warps 3 supplied from a warping bobbin 2, yarn width expanding means 8 disposed downstream of the yarn width reducing means 4, for expanding the yarn width reduced, an ink nozzle 6 interposed between the yarn width reducing means 4 and the yarn width expanding means 8 and ink nozzle moving means 7 for moving the ink nozzle 6 in a yarn width direction.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.

Abstract: Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.