Patents by Inventor Hiroshi Kagotani

Hiroshi Kagotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040241596
    Abstract: A method of forming resist patterns able to decrease development defects caused by deposition of a resist film or redeposition of semi-insolubles in a development process and rinse process using general systems, and a method of producing a semiconductor device using the same, having lithographic process for exposing an element formation region of the resist film at the optimal exposure amount able to develop the resist film via a mask and exposing the circumference region other than the element formation region at an exposure amount not exceeding that exposure amount able to develop the resist film, due to these exposing, reducing the difference of developability and thickness after development of the resist film by which the resist patterns are formed, reducing the difference of surface conditions in the element formation region and circumference region, and able to smoothly remove development defects formed at the time of rinsing or by high speed rotation.
    Type: Application
    Filed: May 4, 2004
    Publication date: December 2, 2004
    Inventors: Yuko Yamaguchi, Atsushi Someya, Hiroshi Kagotani, Kenichi Oyama, Ryoji Watanabe
  • Publication number: 20030054642
    Abstract: The present invention provides a method of and a system for fabricating a semiconductor device, which are capable of suppressing variations in line widths due to a dependence of a dense/sparse line layout on the line widths within one chip, thereby highly accurately forming micro-patterns on a semiconductor chip or the like. In this method, a numerical aperture of a lens system of an exposure apparatus is adjusted, by a host computer functioning as a numerical aperture adjusting apparatus, so as to reduce variations in line widths of patterns formed in an etching step or resist patterns formed in a photolithography step on the basis of a correlation between the variations in line widths and a dense/sparse line layout for the patterns or a correlation between the variations in line widths and a dense/sparse line layout for the resist patterns.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 20, 2003
    Inventors: Hiroshi Kagotani, Harunobu Hirano, Mitsuo Hama
  • Patent number: 6218313
    Abstract: A process for producing a semiconductor device and an apparatus and a process for obtaining an optimum film thickness, the process for producing a semiconductor device comprising forming a film of a light reflecting material on a semiconductor substrate; coating a positive resist on the film of a light reflecting material; forming a resist pattern from the positive resist; and etching the film of a light reflecting material using the resist pattern as a mask, wherein simulation of light intensity is conducted by using optical constants of the semiconductor substrate, the film of a light reflecting material and the resist obtained by measuring the optical constants thereof, or when optical constants thereof are known, by using the known optical constants, with varying a film thickness of the film of a light reflecting material to plural values, so as to obtain a film thickness of the film of a light reflecting material that makes a light absorption energy at an interface between the film of a light reflecting
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: April 17, 2001
    Assignee: Sony Corporation
    Inventors: Manabu Tomita, Hiroshi Kagotani